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System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)

  • US 8,762,909 B1
  • Filed: 03/12/2013
  • Issued: 06/24/2014
  • Est. Priority Date: 03/12/2013
  • Status: Active Grant
First Claim
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1. A computer-implemented method for register placement in an integrated circuit (IC), comprising:

  • determining with a processor a data path between circuit elements;

    placing at least one register along the data path;

    performing with the processor a static timing analysis on the data path;

    extracting with the processor top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments;

    processing the top-level timing data with the processor to determine whether the extended timing path violates a timing requirement; and

    moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated;

    wherein a timing path segment comprises a driving pin and a receiving pin connected by line segments, the line segments selected by;

    connecting with the processor a plurality of points on a circuit into a plurality of bounding boxes, a first bounding box having the driving pin and a second bounding box having the receiving pin;

    logically combining with the processor the bounding boxes to form a polygon, the polygon having a plurality of segments defined by selected points from the plurality of bounding boxes; and

    the timing path segment chosen by selecting with the processor line segments that form a shortest route between the driving pin and the receiving pin.

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