System and method for automatic timing-based register placement and register location adjustment in an integrated circuit (IC)

• US 8,762,909 B1
• Filed: 03/12/2013
• Issued: 06/24/2014
• Est. Priority Date: 03/12/2013
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Inventors: Koenig, Brady A., Dixon, Stephen L., Gentry, Jason Todd
• Primary Examiner(s): Parihar, Suchin
• Application Number:
  US13/796,078
• Time in Patent Office: 469 Days
• Field of Search: 716/100, 716/108
• US Class Current: 716/108
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/3315 using static timing analysis [STA]
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

An embodiment of a method for register placement in an integrated circuit (IC) includes determining a data path between circuit elements, placing at least one register along the data path, performing a static timing analysis on the data path, extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments; processing the top-level timing data to determine whether the extended timing path violates a timing requirement, and moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated.

Claims

1. A computer-implemented method for register placement in an integrated circuit (IC), comprising:

determining with a processor a data path between circuit elements;

placing at least one register along the data path;

performing with the processor a static timing analysis on the data path;

extracting with the processor top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments;

processing the top-level timing data with the processor to determine whether the extended timing path violates a timing requirement; and

moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated;

wherein a timing path segment comprises a driving pin and a receiving pin connected by line segments, the line segments selected by;

connecting with the processor a plurality of points on a circuit into a plurality of bounding boxes, a first bounding box having the driving pin and a second bounding box having the receiving pin;

logically combining with the processor the bounding boxes to form a polygon, the polygon having a plurality of segments defined by selected points from the plurality of bounding boxes; and

the timing path segment chosen by selecting with the processor line segments that form a shortest route between the driving pin and the receiving pin.

2. The method of claim 1, wherein performing a static timing analysis on the data path comprises obtaining with the processor a timing factor for each timing path segment.

3. The method of claim 1, wherein extracting top-level timing data to develop an extended timing path comprises grouping with the processor the timing path segments into extended timing paths.

4. The method of claim 1, wherein processing the top-level timing data to determine whether the extended timing path violates a timing requirement comprises obtaining with the processor timing slack for each timing path segment.

5. The method of claim 1, wherein moving the at least one register along the data path to satisfy a timing requirement comprises moving the at least one register while satisfying a net timing factor for each timing path segment.

6. A system for register placement in an integrated circuit (IC), comprising:

a data path between circuit elements;

at least one register placed along the data path;

logic for performing a static timing analysis on the data path;

logic for extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments;

logic for processing the top-level timing data to determine whether the extended timing path violates a timing requirement; and

logic for moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated;

wherein a timing path segment comprises a driving pin and a receiving pin connected by line segments, the line segments selected by;

connecting a plurality of points on a circuit design into a plurality of bounding boxes, a first bounding box having the driving pin and a second bounding box having the receiving pin;

logically combining the bounding boxes to form a polygon, the polygon having a plurality of segments defined by selected points from the plurality of bounding boxes; and

the timing path segment chosen by selecting line segments that form a shortest route between the driving pin and the receiving pin.

7. The system of claim 6, wherein performing a static timing analysis on the data path comprises obtaining a timing factor for each timing path segment.

8. The system of claim 6, wherein extracting top-level timing data to develop an extended timing path comprises grouping the timing path segments into extended timing paths.

9. The system of claim 6, wherein processing the top-level timing data to determine whether the extended timing path violates a timing requirement comprises obtaining timing slack for each timing path segment.

10. The system of claim 6, wherein moving the at least one register along the data path to satisfy a timing requirement comprises moving the at least one register while satisfying a net timing factor for each timing path segment.

11. An integrated circuit (IC) assembly, comprising:

an integrated circuit chip having a plurality of circuit elements connected by data paths;

at least one register placed along the data path;

logic for performing a static timing analysis on the data path;

logic for extracting top-level timing data to develop an extended timing path, the extended timing path comprising a plurality of timing path segments;

logic for processing the top-level timing data to determine whether the extended timing path violates a timing requirement; and

logic for moving the at least one register along the data path to satisfy the timing requirement if the timing requirement is violated;

wherein a timing path segment comprises a driving pin and a receiving pin connected by line segments, the line segments selected by;

connecting a plurality of points on a circuit design into a plurality of bounding boxes, a first bounding box having the driving pin and a second bounding box having the receiving pin;

logically combining the bounding boxes to form a polygon, the polygon having a plurality of segments defined by selected points from the plurality of bounding boxes;

the timing path segment chosen by selecting line segments that form a shortest route between the driving pin and the receiving pin.

12. The integrated circuit assembly of claim 11, wherein performing a static timing analysis on the data path comprises obtaining a timing factor for each timing path segment.

13. The integrated circuit assembly of claim 11, wherein extracting top-level timing data to develop an extended timing path comprises grouping the timing path segments into extended timing paths.

14. The integrated circuit assembly of claim 11, wherein processing the top-level timing data to determine whether the extended timing path violates a timing requirement comprises obtaining timing slack for each timing path segment.

15. The integrated circuit assembly of claim 11, wherein moving the at least one register along the route to satisfy a timing requirement comprises moving the at least one register while satisfying a net timing factor for each timing path segment.