Methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness

• US 8,762,914 B2
• Filed: 12/30/2010
• Issued: 06/24/2014
• Est. Priority Date: 07/24/2010
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Fischer, Ed, McSherry, Michael, White, David, Yanagida, Bruce, Shah, Akshat
• Primary Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US12/982,732
• Publication Number:
  US 20120023468A1
• Time in Patent Office: 1,272 Days
• Field of Search: None
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods, systems, and articles of manufacture for constraint verification for implementing electronic circuit designs with electrical awareness. Some embodiments identify or set parasitic constraint(s) and compare the electrical parasitic(s) with corresponding parasitic constraint(s) to determine whether the parasitic constraints are met. Some embodiments first identify, determine, or update the physical data of a component of a partial layout and characterize the electrical parasitics associated with the physical data of the component. Some embodiments identify or determine some schematic level performance constraints and estimate parasitic constraints based on schematic simulation results and the performance constraints; the estimated parasitic constraints are then compared with the corresponding electrical parasitics to determine whether the constraints are satisfied. Some embodiments further map schematic level parasitic constraints to a physical design representation and then compares the mapped parasitic constraints with corresponding electrical constraints to determine whether the mapped constraints are met.

Claims

1. A computer implemented method for constraint verification for implementing an electronic circuit design of an electronic circuit with electrical awareness, comprising:

using at least one processor that is programmed for performing a process that comprises;

identifying, determining, or updating physical data of a component of a, incomplete physical design of the electronic circuit design;

determining a parasitic from a schematic level design of the electronic design, rather than from the incomplete physical design, for the incomplete physical design of the electronic circuit design;

characterizing an electrical parasitic by at least performing incomplete layout extraction on at least some of the physical data of the component in the incomplete physical design; and

ensuring correctness of the physical data of the component in the incomplete physical design before completion of the electronic design from the incomplete physical design to a complete physical design based at least in part upon the parasitic determined from the schematic level design of the electronic design and the electrical parasitic.

2. The computer implemented method of claim 1, the process further comprising:

identifying or receiving a parasitic constraint.

3. The computer implemented method of claim 2, wherein the act of ensuring correctness of the physical data comprises:

determining whether the electrical parasitic meets the parasitic constraint.

4. The computer implemented method of claim 2, the process further comprising:

identifying or creating a schematic design for the electronic circuit;

identifying or receiving a first domain constraint; and

mapping the first domain constraint to a second domain based at least in part on a schematic to physical design representation.

5. The computer implemented method of claim 4, the process further comprising:

comparing the electrical parasitic that is associated with the physical data with the first domain constraint that is mapped.

6. The computer implemented method of claim 2, the process further comprising:

identifying another constraint based on the constraint that is identified or received, wherein a satisfaction of the constraint depends on a satisfaction of the another constraint, or the satisfaction of the another constraint depends on the satisfaction of the constraint.

7. The computer implemented method of claim 1, the process further comprising:

determining an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data.

8. The computer implemented method of claim 7, the process further comprising:

determining whether the adjustment violates another constraint.

9. The computer implemented method of claim 7, the process further comprising:

applying the adjustment to the physical data or to other data related to the electrical parasitic or one or more electrical characteristics of the component.

10. The computer implemented method of claim 7, the process further comprising:

determining whether the adjustment causes one or more violations of one or more design rules or one or more constraints.

11. The computer implemented method of claim 10, the process further comprising:

displaying a hint based at least in part upon the adjustment to a user.

12. The computer implemented method of claim 11, the hint is generated for application of the adjustment or for fixing the one or more violations.

13. The computer implemented method of claim 1, the process further comprising:

determining a hint based at least in part upon a result of the act of ensuring the correctness of the physical data; and

displaying the hint in a user interface on a display apparatus.

14. The computer implemented method of claim 1, the process further comprising:

providing a user with a capability to manually set up a constraint on the physical data, the electrical parasitic, or the electrical characteristic.

15. The computer implemented method of claim 1, in which the incomplete physical design does not pass a layout versus schematic check or verification.

16. The computer implemented method of claim 1, in which the act of characterizing the electrical parasitic is performed before or at a time of completing creation of a net or modification of an existing net.

17. The computer implemented method of claim 1, the process further comprising:

verifying an electrical characteristic associated with the component along a net or a partial net after completion of creation or modification of the net or the partial net and before creation or modification of a second net in the incomplete physical design.

18. The computer implemented method of claim 1, in which the act of characterizing the electrical parasitic or the act of characterizing the electrical characteristic is performed based at least in part upon a geometric shape or a set of geometric shapes on a net at a time when the net is created or completed.

19. A system for constraint verification for implementing an electronic circuit design of an electronic circuit with electrical awareness, comprising:

at least one processor that is at least to;

identify, determine, or update physical data of a component of a incomplete physical design of the electronic circuit design;

determine a parasitic from a schematic level design of the electronic design, rather than from the incomplete physical design, for the incomplete physical design of the electronic circuit design;

characterize an electrical parasitic by at least performing incomplete layout extraction on at least some of the physical data of the component in the incomplete physical design; and

ensure correctness of the physical data of the component in the incomplete physical design before completion of the electronic design from the incomplete physical design to a complete physical design based at least in part upon the parasitic determined from the schematic level design of the electronic design and the electrical parasitic.

20. The system of claim 19, the at least one processor is further to:

identify or receive a parasitic constraint;

identify or create a schematic design for the electronic circuit;

identify or receive a first domain constraint; and

map the first domain constraint to a second domain based at least in part on a schematic to physical design representation.

21. The system of claim 19, the at least one processor is further to:

determine a hint based at least in part upon a result of the act of ensuring the correctness of the physical data;

determine an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data;

determine whether the adjustment violates another constraint; and

apply the adjustment to the physical data or to other data related to the electrical parasitic or one or more electrical characteristics associated with the component.

22. The system of claim 19, in which the incomplete physical design does not pass a layout versus schematic check or verification.

23. The system of claim 19, in which the at least one processor is to characterize the electrical parasitic before or at a time of completing creation of a net or modification of an existing net to which the component belongs.

24. The system of claim 19, wherein the at least one processor is further to:

verify an electrical characteristic associated with the component along a net or a partial net after completion of creation or modification of the net or the partial net and before creation or modification of a second net in the incomplete physical design.

25. An article of manufacture comprising a tangible non-transitory computer readable storage medium having a sequence of instructions stored thereupon which, when executed by at least one processor, causes the at least one processor to perform a method for constraint verification for implementing an electronic circuit design of an electronic circuit with electrical awareness, the method comprising:

using the at least one processor that is programmed or configured for performing a process that comprises;

identifying, determining, or updating physical data of a component of a incomplete physical design of the electronic circuit design;

determining a parasitic from a schematic level design of the electronic design, rather than from the incomplete physical design, for the incomplete physical design of the electronic circuit design;

characterizing an electrical parasitic by at least performing incomplete layout extraction on at least some of the physical data of the component in the incomplete physical design; and

ensuring correctness of the physical data of the component in the incomplete physical design before completion of the electronic design from the incomplete physical design to a complete physical design based at least in part upon the parasitic determined from the schematic level design of the electronic design and the electrical parasitic.

26. The article of manufacture of claim 25, the process further comprising:

identifying or receiving a parasitic constraint;

identifying or creating a schematic design for the electronic circuit;

identifying or receiving a first domain constraint; and

mapping the first domain constraint to a second domain based at least in part on a schematic to physical design representation.

27. The article of manufacture of claim 25, the process further comprising:

determining a hint based at least in part upon a result of the act of ensuring the correctness of the physical data;

determining an adjustment based at least in part upon a result of the act of ensuring the correctness of the physical data;

determining whether the adjustment causes one or more violations of another constraint; and

applying the adjustment to the physical data or to other data related to the electrical parasitic or one or more electrical characteristics associated with the component.

28. The article of manufacture of claim 25, in which the incomplete physical design does not pass a layout versus schematic check or verification.

29. The article of manufacture of claim 25, in which the act of characterizing the electrical parasitic is performed before or at a time of completing creation of a net or modification of an existing net.

30. The article of manufacture of claim 25, the process further comprising:

verifying an electrical characteristic associated with the component along a net or a partial net after completion of creation or modification of the net or the partial net and before creation or modification of a second net in the incomplete physical design.