Prefetching irregular data references for software controlled caches
First Claim
1. A method, in a data processing system, for prefetching irregular memory references into a software controlled cache, the method comprising:
- receiving source code that is to be compiled;
analyzing the source code to identify at least one of a plurality of loops that contain an irregular memory reference;
determining whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization;
responsive to an indication that the irregular memory reference may be optimized, determining whether the irregular memory reference is valid for prefetching, wherein determining whether the irregular memory reference is valid for prefetching comprises;
back-slicing the address of the irregular memory reference to determine whether a computed address for the irregular memory reference contains a cache reference thereby forming a back-sliced address; and
responsive to the back-sliced address failing to contain the cache reference, indicating the irregular memory reference as valid for prefetching;
responsive to an indication that the irregular memory reference is valid for prefetching, inserting a store statement for an address of the irregular memory reference into the at least one of the plurality of loops; and
inserting a runtime library call into a prefetch runtime library for the irregular memory reference, wherein data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.
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Abstract
Prefetching irregular memory references into a software controlled cache is provided. A compiler analyzes source code to identify at least one of a plurality of loops that contain an irregular memory reference. The compiler determines if the irregular memory reference within the at least one loop is a candidate for optimization. Responsive to an indication that the irregular memory reference may be optimized, the compiler determines if the irregular memory reference is valid for prefetching. Responsive to an indication that the irregular memory reference is valid for prefetching, a store statement for an address of the irregular memory reference is inserted into the at least one loop. A runtime library call is inserted into a prefetch runtime library for the irregular memory reference. Data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked.
44 Citations
14 Claims
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1. A method, in a data processing system, for prefetching irregular memory references into a software controlled cache, the method comprising:
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receiving source code that is to be compiled; analyzing the source code to identify at least one of a plurality of loops that contain an irregular memory reference; determining whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization; responsive to an indication that the irregular memory reference may be optimized, determining whether the irregular memory reference is valid for prefetching, wherein determining whether the irregular memory reference is valid for prefetching comprises; back-slicing the address of the irregular memory reference to determine whether a computed address for the irregular memory reference contains a cache reference thereby forming a back-sliced address; and responsive to the back-sliced address failing to contain the cache reference, indicating the irregular memory reference as valid for prefetching; responsive to an indication that the irregular memory reference is valid for prefetching, inserting a store statement for an address of the irregular memory reference into the at least one of the plurality of loops; and inserting a runtime library call into a prefetch runtime library for the irregular memory reference, wherein data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked. - View Dependent Claims (2, 3, 4, 5)
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6. A computer program product comprising a non-transitory computer readable storage medium storing a computer readable program recorded thereon, wherein the computer readable program, when executed on a computing device, causes the computing device to:
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receive source code that is to be compiled; analyze the source code to identify at least one of a plurality of loops that contain an irregular memory reference; determine whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization; responsive to an indication that the irregular memory reference may be optimized, determine whether the irregular memory reference is valid for prefetching, wherein the computer readable program to determine whether the irregular memory reference is valid for prefetching further comprises computer readable program that causes the computing device to; back-slice the address of the irregular memory reference to determine whether a computed address for the irregular memory reference contains a cache reference thereby forming a back-sliced address; and responsive to the back-sliced address failing to contain the cache reference, indicate the irregular memory reference as valid for prefetching; responsive to an indication that the irregular memory reference is valid for prefetching, insert a store statement for an address of the irregular memory reference into the at least one of the plurality of loops; and insert a runtime library call into a prefetch runtime library for the irregular memory reference, wherein data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked. - View Dependent Claims (7, 8, 9, 10)
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11. An apparatus, comprising:
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a processor; and a memory coupled to the processor, wherein the memory comprises instructions which, when executed by the processor, cause the processor to; receive source code that is to be compiled; analyze the source code to identify at least one of a plurality of loops that contain an irregular memory reference; determine whether the irregular memory reference within the at least one of the plurality of loops is a candidate for optimization; responsive to an indication that the irregular memory reference may be optimized, determine whether the irregular memory reference is valid for prefetching, wherein the instructions to determine whether the irregular memory reference is valid for prefetching further cause the processor to; back-slice the address of the irregular memory reference to determine whether a computed address for the irregular memory reference contains a cache reference thereby forming a back-sliced address; and responsive to the back-sliced address failing to contain the cache reference, indicate the irregular memory reference as valid for prefetching; responsive to an indication that the irregular memory reference is valid for prefetching, insert a store statement for an address of the irregular memory reference into the at least one of the plurality of loops; and insert a runtime library call into a prefetch runtime library for the irregular memory reference, wherein data associated with the irregular memory reference is prefetched into the software controlled cache when the runtime library call is invoked. - View Dependent Claims (12, 13, 14)
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Specification