Semiconductor diodes fabricated by aspect ratio trapping with coalesced films

• US 8,765,510 B2
• Filed: 10/12/2012
• Issued: 07/01/2014
• Est. Priority Date: 01/09/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lochtefeld, Anthony J.
• Primary Examiner(s): LE, DUNG ANH
• Application Number:
  US13/650,206
• Publication Number:
  US 20130034924A1
• Time in Patent Office: 627 Days
• Field of Search: 438 47- 48, 438 50- 52, 438/22, 257 14- 16, 257/79, 257/86, 257/88, 257/94, 257/96, 257/103, 257/101, 257/431, 257/458, 257/461, 257/E33.008, 257/E33.032, 257/E29.328, 257/E39.339, 257/E29.336
• US Class Current: 438/47
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02543 Phosphides
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02573 Conductivity type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02647 Lateral overgrowth
• CPC Class Codes: H01L 21/187 by direct bonding
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/151 Compositional structures H01L29/157 and H01L29/158 take precedence
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/882 Resonant tunneling diodes, i.e. RTD, RTBD
• CPC Class Codes: H01L 2933/005 relating to encapsulations
• CPC Class Codes: H01L 31/1852 comprising a growth substrate not being an AIIIBV compound
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/52 Encapsulations
• CPC Class Codes: Y02E 10/543 : Solar cells from Group II-VI materials
• CPC Class Codes: Y02E 10/544 : Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/548 : Amorphous silicon PV cells
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A photonic device comprises a substrate and a dielectric material including two or more openings that expose a portion of the substrate, the two or more openings each having an aspect ratio of at least 1. A bottom diode material comprising a compound semiconductor material that is lattice mismatched to the substrate occupies the two or more openings and is coalesced above the two or more openings to form the bottom diode region. The device further includes a top diode material and an active diode region between the top and bottom diode materials.

Claims

1. A method comprising:

depositing a layer of a dielectric material onto a substrate;

patterning two or more openings in the dielectric material to expose respective portions of a surface of the substrate, the two or more openings having an aspect ratio of at least 1;

forming a bottom diode region by growing a compound semiconductor material that is lattice mismatched to a crystalline material of the substrate in the two or more openings, the compound semiconductor material adjoining the crystalline material, and allowing the compound semiconductor material to fill the two or more openings and coalesce above the two or more openings to form a continuous layer;

forming an active diode region on the bottom diode region; and

forming a top diode region on the active diode region.

2. The method of claim 1 further comprising:

bonding a handle substrate to the top diode region; and

removing the substrate.

3. The method of claim 1 further comprising:

implanting ions into the continuous layer of the compound semiconductor material to create a cleavage plane;

bonding a handle substrate to the continuous layer of the compound semiconductor material; and

cleaving the continuous layer of the compound semiconductor material at the cleavage plane.

4. The method of claim 1 further comprising forming a divot in the continuous layer of the compound semiconductor material.

5. The method of claim 1, wherein the continuous layer of the compound semiconductor material has a dislocation density less than or equal to 10⁸ cm⁻

2.

6. The method of claim 1, wherein the compound semiconductor material comprises dislocations, the dislocations terminating at respective sidewalls of the openings.

7. The method of claim 1 further comprising:

masking the top diode region, the active diode region, and the bottom diode region; and

while the top diode region, the active diode region, and the bottom diode region are masked;

patterning two or more additional openings in the dielectric material to expose respective portions of the surface of the substrate;

forming an additional bottom diode region by growing an additional compound semiconductor material in the two or more additional openings and allowing the additional compound semiconductor material to fill the two or more additional openings and coalesce above the two or more additional openings to form an additional continuous layer;

forming an additional active diode region on the additional bottom diode region; and

forming an additional top diode region on the additional active diode region.

8. A method comprising:

depositing a layer of a dielectric material on a substrate;

patterning two or more openings in the dielectric material to expose portions of a surface of the substrate, the two or more openings having an aspect ratio of at least 1;

forming a bottom diode region by;

growing a compound semiconductor material in the two or more openings, the compound semiconductor material being lattice mismatched to a crystalline material of the substrate in the portions of the surface of the substrate, and

growing the compound semiconductor material to coalesce above a top surface of the dielectric material between the two or more openings to form a continuous layer;

forming an active diode region on the bottom diode region;

forming a top diode region on the active diode region;

bonding a handle substrate to the top diode region; and

removing the substrate.

9. The method of claim 8 further comprising removing the dielectric material.

10. The method of claim 8 further comprising:

contacting a first electrical contact with the handle substrate; and

contacting a second electrical contact with the bottom diode region.

11. The method of claim 8, wherein the removing the substrate comprises cleaving the continuous layer at a cleavage plane.

12. The method of claim 8, wherein the removing the substrate comprises grinding the substrate.

13. The method of claim 8, wherein the continuous layer of the compound semiconductor material has a dislocation density less than or equal to 10⁸ cm⁻

2.

14. The method of claim 8, wherein the compound semiconductor material comprises dislocations, the dislocations terminating at respective sidewalls of the openings.

15. A method comprising:

depositing a layer of dielectric material on a substrate;

patterning a first set of openings in the layer of dielectric material to expose first portions of a surface of the substrate, the first set of openings having an aspect ratio of at least 1;

forming a first bottom diode region by growing a first semiconductor material that is lattice mismatched to a crystalline material of the substrate in the first set of openings and growing the first semiconductor material to coalesce above the layer of dielectric material and between respective ones of the first set of openings to form a first continuous layer;

forming a first active diode region on the first bottom diode region;

forming a first top diode region on the first active diode region;

masking the first bottom diode region, first active diode region, and first top diode region;

patterning a second set of openings in the layer of dielectric material to expose second portions of the surface of the substrate, the second set of openings having an aspect ratio of at least 1;

forming a second bottom diode region by growing a second semiconductor material that is lattice mismatched to the crystalline material of the substrate in the second set of openings and growing the second semiconductor material to coalesce above the layer of dielectric material and between respective ones of the second set of openings to form a second continuous layer;

forming a second active diode region on the second bottom diode region; and

forming a second top diode region on the second active diode region.

16. The method of claim 15 further comprising:

contacting a first electrical contact with the substrate;

contacting a second electrical contact with first top diode region; and

contacting a third electrical contact with the second top diode region.

17. The method of claim 15, wherein the first semiconductor material and the second semiconductor material are different materials.

18. The method of claim 15, wherein a bandgap of the first active diode region is different from a bandgap of the second active diode region.

19. The method of claim 15, wherein the first semiconductor material comprises first dislocations arising from the lattice mismatch with the crystalline material of the substrate, the first dislocations terminating at respective first sidewalls of the first set of openings, and wherein the second semiconductor material comprises second dislocations arising from the lattice mismatch with the crystalline material of the substrate, the second dislocations terminating at respective second sidewalls of the second set of openings.

20. The method of claim 15, wherein each of the first continuous layer and the second continuous layer has a dislocation density less than or equal to 10⁸ cm⁻

2.