Stacked oxide material, semiconductor device, and method for manufacturing the semiconductor device

• US 8,765,522 B2
• Filed: 11/22/2010
• Issued: 07/01/2014
• Est. Priority Date: 11/28/2009
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Chambliss, Alonzo
• Application Number:
  US12/951,225
• Publication Number:
  US 20110127579A1
• Time in Patent Office: 1,317 Days
• Field of Search: 438/104, 438/149, 438/151, 438/156, 438/158, 438/159, 438/268, 438/283, 257/43, 257/52, 257/57, 257/59, 257/66, 257/72, 257/192
• US Class Current: 438/104
• CPC Class Codes: H01L 21/02472 Oxides
• CPC Class Codes: H01L 21/02483 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 21/16 the devices having semiconductor bodies comprising cuprous oxide or cuprous iodide
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: Y10T 156/10 Methods of surface bonding and/or assembly therefor
• CPC Class Codes: Y10T 428/265 1 mil or less
• CPC Class Codes: Y10T 428/31678 Of metal

Abstract

One embodiment is a method for manufacturing a stacked oxide material, including the steps of forming a first oxide component over a base component, causing crystal growth which proceeds from a surface toward an inside of the first oxide component by first heat treatment to form a first oxide crystal component at least partly in contact with the base component, forming a second oxide component over the first oxide crystal component; and causing crystal growth by second heat treatment using the first oxide crystal component as a seed to form a second oxide crystal component.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer including a flat surface over a surface of a base;

forming a gate insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer over the gate insulating layer;

causing crystal growth which proceeds from a surface toward an inside of the first oxide semiconductor layer by first heat treatment to form a first single crystal layer;

forming a second oxide semiconductor layer over the first single crystal layer;

causing crystal growth which proceeds from the first single crystal layer toward a surface of the second oxide semiconductor layer thereover by second heat treatment to form a second single crystal layer; and

forming a source electrode layer and a drain electrode layer over a stack of the first single crystal layer and the second single crystal layer.

2. The method for manufacturing a semiconductor device, according to claim 1,

wherein the source electrode layer or the drain electrode layer overlaps with an edge portion and a portion of the flat surface of the gate electrode layer.

3. The method for manufacturing a semiconductor device, according to claim 1, wherein the first single crystal layer has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

4. The method for manufacturing a semiconductor device, according to claim 1,

wherein the second single crystal layer has an a-b plane in a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

5. The method for manufacturing a semiconductor device, according to claim 1, wherein the second oxide semiconductor layer has a larger thickness than the first oxide semiconductor layer.

6. The method for manufacturing a semiconductor device, according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer have a same electron affinity.

7. The method for manufacturing a semiconductor device, according to claim 1, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed using different materials.

8. A semiconductor device comprising:

a gate electrode layer including a flat surface over a surface of a base;

a gate insulating layer over the gate electrode layer;

a first single crystal layer which is over and at least partly in contact with the gate insulating layer, has an a-b plane along a surface thereof and c-axis-aligned perpendicularly to the surface thereof;

a second single crystal layer which is over and in contact with the first single crystal layer, has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof; and

a source electrode layer and a drain electrode layer over a stack of the first single crystal layer and the second single crystal layer,

wherein the first single crystal layer and the second single crystal layer are metal oxide layers.

9. The semiconductor device according to claim 8, wherein the second single crystal layer has a larger thickness than the first single crystal layer.

10. The semiconductor device according to claim 8, wherein the first single crystal layer and the second single crystal layer have a same electron affinity.

11. The semiconductor device according to claim 8, wherein the first single crystal layer and the second single crystal layer are formed using different materials.

12. The semiconductor device according to claim 8, wherein a difference in height at a region in the surface of the second single crystal layer which overlaps with the gate electrode layer is less than or equal to 1 nm.

13. The semiconductor device according to claim 8, wherein a difference in height at a region in the surface of the second single crystal layer which overlaps with the gate electrode layer is less than or equal to 0.2 nm.

14. The semiconductor device according to claim 8, wherein the first single crystal layer and the second single crystal layer are one single crystal.

15. A semiconductor device comprising:

a gate electrode layer including a flat surface over a surface of a base;

a gate insulating layer over the gate electrode layer;

a first single crystal layer which is over and at least partly in contact with the gate insulating layer, has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof;

a second single crystal layer which is on and in contact with the first single crystal layer, has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof; and

a source electrode layer and a drain electrode layer over a stack of the first single crystal layer and the second single crystal layer,

wherein the source electrode layer or the drain electrode layer is provided so as to overlap with a portion of the flat surface of the gate electrode layer.

16. The semiconductor device according to claim 15, wherein the second single crystal layer has a larger thickness than the first single crystal layer.

17. The semiconductor device according to claim 15, wherein the first single crystal layer and the second single crystal layer have a same electron affinity.

18. The semiconductor device according to claim 15, wherein the first single crystal layer and the second single crystal layer are formed using different materials.

19. The semiconductor device according to claim 15, wherein a difference in height at a region in the surface of the second single crystal layer which overlaps with the gate electrode layer is less than or equal to 1 nm.

20. The semiconductor device according to claim 15, wherein a difference in height at a region in the surface of the second single crystal layer which overlaps with the gate electrode layer is less than or equal to 0.2 nm.

21. The semiconductor device according to claim 15, wherein the first single crystal layer and the second single crystal layer are one single crystal.

22. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first oxide semiconductor layer over a substrate;

causing crystal growth which proceeds from a surface toward an inside of the first oxide semiconductor layer by heat treatment, wherein a crystal layer is formed at the surface of the first oxide semiconductor layer; and

forming a second oxide semiconductor layer over the first oxide semiconductor layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, zinc and a metal other than indium and zinc.

23. The method for manufacturing a semiconductor device according to claim 22, wherein the crystal layer has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

24. The method for manufacturing a semiconductor device according to claim 22, wherein the second oxide semiconductor layer has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

25. The method for manufacturing a semiconductor device according to claim 22, wherein the metal other than indium and zinc includes gallium.

26. The method for manufacturing a semiconductor device according to claim 22, wherein the first oxide semiconductor layer has a thickness of greater than or equal to 2 nm and less than or equal to 15 nm.

27. The method for manufacturing a semiconductor device according to claim 22, wherein the heat treatment is performed in a nitrogen atmosphere, an oxygen atmosphere, or a dry air atmosphere at a temperature higher than or equal to 450°

C. and lower than or equal to 850°

C.

28. The method for manufacturing a semiconductor device according to claim 22, wherein the crystal layer is a single crystal layer.

29. The method for manufacturing a semiconductor device according to claim 22, wherein a hydrogen concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹⁸ cm<sup>−

3</sup>.

30. The method for manufacturing a semiconductor device according to claim 22, wherein a carrier concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹² cm<sup>−

3</sup>.

31. The method for manufacturing a semiconductor device according to claim 22, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer has high purity and has an intrinsic conductivity type.

32. The method for manufacturing a semiconductor device according to claim 22, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed using different materials.

33. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first oxide semiconductor layer over a substrate;

causing crystal growth which proceeds from a surface toward an inside of the first oxide semiconductor layer by first heat treatment, wherein a crystal layer is formed at the surface of the first oxide semiconductor layer; and

forming a second oxide semiconductor layer over the first oxide semiconductor layer;

causing crystal growth of the second oxide semiconductor layer by second heat treatment using the crystal layer as a seed;

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, zinc and a metal other than indium and zinc.

34. The method for manufacturing a semiconductor device according to claim 33, wherein the crystal layer has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

35. The method for manufacturing a semiconductor device according to claim 33, wherein the second oxide semiconductor layer has an a-b plane along a surface thereof and is c-axis-aligned perpendicularly to the surface thereof.

36. The method for manufacturing a semiconductor device according to claim 33, wherein the metal other than indium and zinc includes gallium.

37. The method for manufacturing a semiconductor device according to claim 33, wherein the first oxide semiconductor layer has a thickness of greater than or equal to 2 nm and less than or equal to 15 nm.

38. The method for manufacturing a semiconductor device according to claim 33, wherein the first heat treatment and the second heat treatment are each performed in a nitrogen atmosphere, an oxygen atmosphere, or a dry air atmosphere at a temperature higher than or equal to 450°

C. and lower than or equal to 850°

C.

39. The method for manufacturing a semiconductor device according to claim 33, wherein the crystal growth of the second oxide semiconductor layer proceeds from the surface of the first oxide semiconductor layer toward a surface of the second oxide semiconductor layer.

40. The method for manufacturing a semiconductor device according to claim 33, wherein the crystal layer is a single crystal layer.

41. The method for manufacturing a semiconductor device according to claim 33, wherein a hydrogen concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹⁸ cm<sup>−

3</sup>.

42. The method for manufacturing a semiconductor device according to claim 33, wherein a carrier concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹² cm<sup>−

3</sup>.

43. The method for manufacturing a semiconductor device according to claim 33, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer has high purity and has an intrinsic conductivity type.

44. The method for manufacturing a semiconductor device according to claim 33, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed using different materials.

45. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first oxide semiconductor layer over a substrate by a sputtering method;

performing first heat treatment to the first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer by a sputtering method, wherein the substrate is heated during deposition of the second oxide semiconductor layer;

performing second heat treatment to the second oxide semiconductor layer;

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, zinc and a metal other than indium and zinc.

46. The method for manufacturing a semiconductor device according to claim 45, wherein a crystal growth of the first oxide semiconductor layer is caused by the first heat treatment.

47. The method for manufacturing a semiconductor device according to claim 45, wherein a crystal growth of the second oxide semiconductor layer is caused by the second heat treatment.

48. The method for manufacturing a semiconductor device according to claim 45, wherein the metal other than indium and zinc includes gallium.

49. The method for manufacturing a semiconductor device according to claim 45, wherein the first oxide semiconductor layer has a thickness of greater than or equal to 2 nm and less than or equal to 15 nm.

50. The method for manufacturing a semiconductor device according to claim 45, wherein the first heat treatment and the second heat treatment are each performed in a nitrogen atmosphere, an oxygen atmosphere, or a dry air atmosphere at a temperature higher than or equal to 450°

C. and lower than or equal to 850°

C.

51. The method for manufacturing a semiconductor device according to claim 45, wherein the heating of the substrate during the deposition of the second oxide semiconductor layer is performed at a temperature higher than or equal to 200°

C. and lower than or equal to 600°

C.

52. The method for manufacturing a semiconductor device according to claim 45, wherein a hydrogen concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹⁸ cm<sup>−

3</sup>.

53. The method for manufacturing a semiconductor device according to claim 45, wherein a carrier concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹² cm<sup>−

3</sup>.

54. The method for manufacturing a semiconductor device according to claim 45, wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer has high purity and has an intrinsic conductivity type.

55. The method for manufacturing a semiconductor device according to claim 45, wherein the first oxide semiconductor layer and the second oxide semiconductor layer are formed using different materials.

56. A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate electrode layer over a substrate;

forming an insulating layer over the gate electrode layer;

forming a first oxide semiconductor layer over the insulating layer;

performing first heat treatment to the first oxide semiconductor layer;

forming a second oxide semiconductor layer over the first oxide semiconductor layer, wherein the substrate is heated during deposition of the second oxide semiconductor layer; and

performing second heat treatment to the second oxide semiconductor layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise a region overlapping with the gate electrode layer, and

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, zinc and a metal other than indium and zinc.

57. The method for manufacturing a semiconductor device according to claim 56, further comprising a step of forming a source electrode and a drain electrode which are electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer.

58. The method for manufacturing a semiconductor device according to claim 56, wherein the heating of the substrate during the deposition of the second oxide semiconductor layer is performed at a temperature higher than or equal to 200°

C. and lower than or equal to 600°

C.

59. The method for manufacturing a semiconductor device according to claim 56, wherein a hydrogen concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹⁸ cm<sup>−

3</sup>.

60. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first gate electrode layer over a substrate;

forming a first insulating layer over the first gate electrode layer;

forming a first oxide semiconductor layer over the first insulating layer;

performing first heat treatment;

forming a second oxide semiconductor layer over the first oxide semiconductor layer, wherein the substrate is heated during deposition of the second oxide semiconductor layer;

performing second heat treatment;

forming a second insulating layer over the second oxide semiconductor layer; and

forming a second gate electrode layer over the second insulating layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise a region overlapping with the first gate electrode layer,

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise a region overlapping with the second gate electrode layer, and

wherein the first oxide semiconductor layer and the second oxide semiconductor layer each comprise indium, zinc and a metal other than indium and zinc.

61. The method for manufacturing a semiconductor device according to claim 60, further comprising a step of forming a source electrode and a drain electrode which are electrically connected to the first oxide semiconductor layer and the second oxide semiconductor layer.

62. The method for manufacturing a semiconductor device according to claim 60, wherein the heating of the substrate during the deposition of the second oxide semiconductor layer is performed at a temperature higher than or equal to 200°

C. and lower than or equal to 600°

C.

63. The method for manufacturing a semiconductor device according to claim 60, wherein a hydrogen concentration of each of the first oxide semiconductor layer and the second oxide semiconductor layer is less than 1×

10¹⁸ cm<sup>−

3</sup>.