Method for fabricating semiconductor device

• US 8,765,561 B2
• Filed: 06/06/2011
• Issued: 07/01/2014
• Est. Priority Date: 06/06/2011
• Status: Active Grant

• Current Assignee: Marlin Semiconductor Limited (f/k/a Sandyford Semiconductor Limited) (Vector Capital Corporation)
• Original Assignee: United Microelectronics Corporation
• Inventors: Hung, Wen-Han, Chen, Tsai-Fu, Lo, Ta-Kang, Cheng, Tzyy-Ming
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US13/154,396
• Publication Number:
  US 20120309158A1
• Time in Patent Office: 1,121 Days
• Field of Search: 438/308, 438/795, 438/799, 257/E21.623, 257/E21.444, 257/E21.453, 257/E21.434
• US Class Current: 438/308
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a dummy gate on the substrate; forming a contact etch stop layer on the dummy gate and the substrate; performing a planarizing process to partially remove the contact etch stop layer; partially removing the dummy gate; and performing a thermal treatment on the contact etch stop layer.

Claims

1. A method for fabricating semiconductor device, comprising:

providing a substrate;

forming a dummy gate on the substrate;

forming a contact etch stop layer on the dummy gate and the substrate, wherein the contact etch stop layer comprises a tensile stress layer;

forming an interlayer dielectric layer on the tensile stress layer;

performing a planarizing process to partially remove the interlayer dielectric layer and the contact etch stop layer;

partially removing the dummy gate; and

after removing the dummy gate, performing a thermal treatment on both the contact etch stop layer and the interlayer dielectric layer.

2. The method of claim 1, wherein the planarizing process comprises a chemical mechanical polishing process.

3. The method of claim 1, wherein the thermal treatment comprises a spike anneal process.

4. The method of claim 1, wherein the thermal treatment comprises a millisecond anneal process.

5. The method of claim 1, wherein the thermal treatment comprises a UV curing process.

6. The method of claim 1, wherein the contact etch stop layer is a tensile stress contact etch stop layer.

7. The method of claim 1, wherein the semiconductor device comprises an NMOS transistor.

8. The method of claim 1, wherein the contact etch stop layer comprises a thickness between 50 Angstroms to 200 Angstroms.

9. The method of claim 1, wherein the dummy gate comprises an interfacial layer, a high-k dielectric layer, and a polysilicon layer.

10. The method of claim 9, further comprising:

forming a source/drain region in the substrate adjacent to two sides of the dummy gate before forming the contact etch stop layer;

forming a silicide layer on the source/drain region;

covering an interlayer dielectric layer on the contact etch stop layer;

removing the polysilicon layer of the dummy gate to form a recess in the interlayer dielectric layer;

performing the thermal treatment on the contact etch stop layer; and

depositing a work function layer, a barrier layer, and a conductive layer in the recess for forming a gate.

11. The method of claim 10, wherein after forming the gate further comprises:

forming a plurality of contact vias in the dielectric layer; and

forming a silicide layer in the contact vias.

12. The method of claim 1, further comprising forming a spacer on the sidewall of the dummy gate.

13. The method of claim 12, further comprising forming the contact etch stop layer on the dummy gate, the substrate, and the spacer.

14. The method of claim 1, further comprising:

forming a source/drain region in the substrate adjacent to two sides of the dummy gate before forming the contact etch stop layer;

forming a silicide layer on the source/drain region;

covering an interlayer dielectric layer on the contact etch stop layer;

partially removing the dummy gate to form a recess in the interlayer dielectric layer;

performing the thermal treatment on the contact etch stop layer; and

forming a gate in the recess, wherein the gate comprises a high-k dielectric layer, a work function layer, a barrier layer, and a conductive layer.

15. The method of claim 14, wherein the high-k dielectric layer comprises a U-shaped high-k dielectric layer.

16. The method of claim 14, wherein after forming the gate further comprises:

forming a plurality of contact vias in the dielectric layer; and

forming a silicide layer in the contact vias.