Method of fabricating thermally controlled refractory metal resistor

• US 8,765,568 B2
• Filed: 10/08/2013
• Issued: 07/01/2014
• Est. Priority Date: 12/08/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Lukaitis, Joseph M., Massey, Deborah M., Sullivan, Timothy D., Wang, Ping-Chuan, Watson, Kimball M.
• Primary Examiner(s): Smoot, Stephen W
• Application Number:
  US14/048,629
• Publication Number:
  US 20140038381A1
• Time in Patent Office: 266 Days
• Field of Search: 257/E23.109
• US Class Current: 438/384
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 27/0211 adapted for requirements of temperature
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/24 with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A structure and method of fabricating the structure includes a semiconductor substrate having a top surface defining a horizontal direction and a plurality of interconnect levels stacked from a lowermost level proximate the top surface of the semiconductor substrate to an uppermost level furthest from the top surface. Each of the interconnect levels include vertical metal conductors physically connected to one another in a vertical direction perpendicular to the horizontal direction. The vertical conductors in the lowermost level being physically connected to the top surface of the substrate, and the vertical conductors forming a heat sink connected to the semiconductor substrate. A resistor is included in a layer immediately above the uppermost level. The vertical conductors being aligned under a downward vertical resistor footprint of the resistor, and each interconnect level further include horizontal metal conductors positioned in the horizontal direction and being connected to the vertical conductors.

Claims

1. A method of fabrication of a semiconductor structure, said method comprising:

providing a semiconductor substrate having a top surface, said top surface defining a horizontal direction;

stacking a plurality of interconnect levels on said top surface of said semiconductor substrate to form a heat sink, said stacking further comprising forming vertical metal conductors and horizontal metal conductors in each of said interconnect levels; and

providing a resistor in a layer immediately above an uppermost level of said plurality of interconnect levels such that a downward vertical resistor footprint of said resistor is substantially aligned over said plurality of interconnect levels.

2. The method of fabrication of claim 1, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning an array of integrally formed parallel wires and vias.

3. The method of fabrication of claim 2, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

vertically aligning each of said vias in a vertical direction with other vias of adjacent levels.

4. The method of fabrication of claim 1, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning a horizontal two-dimensional array including a metal plate having fill shape vias.

5. The method of fabrication of claim 4, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

vertically aligning each of said fill shape vias in a vertical direction with other fill shape vias of adjacent levels.

6. The method of fabrication of claim 1, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning said vertical metal conductors and said horizontal metal conductors completely inside said downward vertical resistor footprint of said resistor.

7. The method of fabrication of claim 1, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning said vertical metal conductors and said horizontal metal conductors outside said downward vertical resistor footprint of said resistor by progressively increasing the lateral width of said vertical metal conductors and said horizontal metal conductors from an uppermost level of said plurality of interconnect levels to a lowermost level of said plurality of interconnect levels, said lowermost level being proximate said semiconductor substrate.

8. A method of fabricating a semiconductor structure, said method comprising:

providing a semiconductor substrate having a top surface, said top surface defining a horizontal direction;

stacking a plurality of interconnect levels on said top surface of said semiconductor substrate to form a heat sink, said stacking further comprising forming vertical metal conductors and horizontal metal conductors in each of said interconnect levels;

providing a resistor in a layer immediately above an uppermost level of said plurality of interconnect levels such that a downward vertical resistor footprint of said resistor is substantially aligned over said plurality of interconnect levels; and

providing a heat shield immediately above and electrically isolated from said resistor, said heat shield substantially inhibiting thermal radiation in an upward vertical direction from said resistor.

9. The method of claim 8, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning an array of integrally formed parallel wires and vias.

10. The method of claim 9, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

vertically aligning each of said vias in a vertical direction with other vias of adjacent levels.

11. The method of claim 8, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning a horizontal two-dimensional array including a metal plate having fill shape vias.

12. The method of claim 11, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

vertically aligning each of said fill shape vias in a vertical direction with other fill shape vias of adjacent levels.

13. The method of claim 8, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning said vertical and horizontal metal conductors completely inside said downward vertical resistor footprint of said resistor.

14. The method of claim 8, said forming said vertical metal conductors and said horizontal metal conductors in each of said interconnect levels further comprising:

aligning said vertical metal conductors and said horizontal metal conductors outside said downward vertical resistor footprint of said resistor by progressively increasing the lateral width of said vertical metal conductors and said horizontal metal conductors from an uppermost level of said plurality of interconnect levels to a lowermost level of said plurality of interconnect levels, said lowermost level being proximate said semiconductor substrate.

15. A method comprising:

providing a semiconductor substrate having a top surface, said top surface defining a horizontal direction;

stacking a first interconnect level on said top surface of said semiconductor substrate;

forming vertical metal conductors and horizontal metal conductors in said first interconnect level, said horizontal metal conductors contacting said vertical metal conductors and said vertical metal conductors contacting said semiconductor substrate;

stacking additional interconnect levels on top of said first interconnect level;

forming vertical metal conductors and horizontal metal conductors in each of said additional interconnect levels, said horizontal metal conductors contacting said vertical metal conductors and said vertical metal conductors contacting said horizontal metal conductors in a next lower interconnect level; and

forming a resistor in a layer immediately above an uppermost level of said additional interconnect levels, a downward vertical footprint of said resistor being substantially aligned over said vertical metal conductors and horizontal metal conductors in said interconnect levels.

16. The method of claim 15, further comprising:

forming a heat shield immediately above said resistor, said heat shield being electrically isolated from said resistor.

17. The method of claim 15, said forming vertical metal conductors and horizontal metal conductors further comprising one of:

aligning an array of integrally formed parallel wires and vias; and

aligning a horizontal two-dimensional array including a metal plate having fill shape vias.

18. The method of claim 17, said forming said vertical metal conductors and said horizontal metal conductors further comprising one of:

vertically aligning said vias in a vertical direction with other vias of adjacent levels; and

vertically aligning each of said fill shape vias in a vertical direction with other fill shape vias of adjacent levels.

19. The method of claim 15, said forming said vertical metal conductors and said horizontal metal conductors further comprising:

aligning said vertical metal conductors and horizontal metal conductors completely inside said downward vertical footprint of said resistor.

20. The method of claim 15, said forming said vertical metal conductors and said horizontal metal conductors further comprising:

aligning said vertical metal conductors and said horizontal metal conductors outside said downward vertical footprint of said resistor by progressively increasing the lateral width of said vertical metal conductors and said horizontal metal conductors from an uppermost level of said interconnect levels to a lowermost level of said interconnect levels, said lowermost level being proximate said semiconductor substrate.