Method of forming a borderless contact structure employing dual etch stop layers

• US 8,765,585 B2
• Filed: 04/28/2011
• Issued: 07/01/2014
• Est. Priority Date: 04/28/2011
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Fan, Su C., Horak, David V., Koburger, Charles W. III, Ponoth, Shom, Yang, Chih-Chao
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): THOMAS, TONIAE M
• Application Number:
  US13/095,955
• Publication Number:
  US 20120273848A1
• Time in Patent Office: 1,160 Days
• Field of Search: 438/586, 438/300, 438/595, 438/637, 438/740, 257/E21.49, 257/E21.577, 257/E21.585, 257/E21.619, 257/E21.627
• US Class Current: 438/586
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41775 characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

Claims

1. A method of forming a semiconductor structure comprising:

forming at least one gate structure on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;

forming a second etch stop layer on said at least one gate structure;

forming a stack of a first contact-level dielectric layer and a second contact-level dielectric layer over said second etch stop layer;

forming at least one gate contact via hole and at least one source/drain contact via hole within said stack of said first and second contact-level dielectric layers;

simultaneously extending said at least one gate contact via hole and said at least one source/drain contact via hole, wherein said at least one source/drain contact via hole is extended through said first contact-level dielectric layer stopping on said second etch stop layer and said at least one gate contact via hole is extended through one of said at least one gate cap dielectric stopping on one of said at least one first etch stop layer, respectively, during said simultaneous extension; and

etching exposed portions of said at least one first etch stop layer in said at least one gate contact via hole and etching exposed portions of said second etch stop layer in said at least one source/drain contact via hole.

2. The method of claim 1, wherein said exposed portions of said at least one first etch stop layer and said exposed portions of said second etch stop layer are etched simultaneously.

3. The method of claim 1, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material that is different from a material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

4. The method of claim 1, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material selected from silicon oxide, silicon nitride, and a dielectric metal oxide.

5. The method of claim 4, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a dielectric metal oxide.

6. The method of claim 5, wherein each of said at least one first etch stop layer and said second etch stop layer is selected from HfO₂, Y₂O₃, and Al₂O₃.

7. The method of claim 5, wherein said at least one first etch stop layer and said second etch stop layer comprise a same dielectric metal oxide.

8. The method of claim 1, wherein said at least one first etch stop layer includes a conductive metallic compound.

9. The method of claim 1, further comprising forming at least one gate spacer on said at least one gate structure, wherein said second etch stop layer is formed directly on said at least one gate spacer, and said at least one source/drain contact via hole stops on an outer surface of said at least one gate spacer after said etching of said exposed portions of said second etch stop layer.

10. The method of claim 1, wherein said at least one gate cap dielectric and said first contact-level dielectric layer comprise a first dielectric material, and said second contact-level dielectric layer comprise a second dielectric material different from said first dielectric material.

11. A method of forming a semiconductor structure comprising:

forming at least one gate structure on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;

forming a second etch stop layer on said at least one gate structure;

forming raised source/drain regions on a top surface of said semiconductor substrate after forming at least one gate spacer on said at least one gate structure and before forming said second etch stop layer;

forming a stack of a first contact-level dielectric layer and a second contact-level dielectric layer over said second etch stop layer;

forming at least one gate contact via hole and at least one source/drain contact via hole within said stack of said first and second contact-level dielectric layers; and

simultaneously extending said at least one gate contact via hole and said at least one source/drain contact via hole, wherein said at least one source/drain contact via hole is extended through said first contact-level dielectric layer stopping on said second etch stop layer and said at least one gate contact via hole is extended through one of said at least one gate cap dielectric stopping on one of said at least one first etch stop layer, respectively, during said simultaneous extension.

12. The method of claim 11, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material that is different from a material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

13. The method of claim 11, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material selected from silicon oxide, silicon nitride, and a dielectric metal oxide.

14. The method of claim 13, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a dielectric metal oxide.

15. The method of claim 11, further comprising etching exposed portions of said second etch stop layer in said at least one source/drain contact via hole, wherein said second etch stop layer is formed directly on said at least one gate spacer, and said at least one source/drain contact via hole stops on an outer surface of said at least one gate spacer after said etching of said exposed portions of said second etch stop layer.

16. A method of forming a semiconductor structure comprising:

forming at least one gate structure on a semiconductor substrate, wherein each of said at least one gate structure includes, from bottom to top, a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric;

forming a second etch stop layer on said at least one gate structure;

forming a stack of a first contact-level dielectric layer and a second contact-level dielectric layer over said second etch stop layer;

forming at least one gate contact via hole and at least one source/drain contact via hole within said stack of said first and second contact-level dielectric layers;

simultaneously extending said at least one gate contact via hole and said at least one source/drain contact via hole, wherein said at least one source/drain contact via hole is extended through said first contact-level dielectric layer stopping on said second etch stop layer and said at least one gate contact via hole is extended through one of said at least one gate cap dielectric stopping on one of said at least one first etch stop layer, respectively, during said simultaneous extension, wherein said at least one gate contact via hole extends through said second and first contact-level dielectric layers and to a surface of said at least one gate cap dielectric before said simultaneous extending of said at least one gate contact via hole and said at least one source/drain contact via hole, and said at least one source/drain contact via hole extends through said second contact-level dielectric layer and does not extend through said first contact-level dielectric layer before said simultaneous extending of said at least one gate contact via hole and said at least one source/drain contact via hole.

17. The method of claim 16, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material that is different from a material of said at least one gate cap dielectric and said first contact-level dielectric material layer.

18. The method of claim 16, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a material selected from silicon oxide, silicon nitride, and a dielectric metal oxide.

19. The method of claim 18, wherein each of said at least one first etch stop layer and said second etch stop layer comprises a dielectric metal oxide.

20. The method of claim 16, further comprising forming at least one gate spacer on said at least one gate structure, wherein said second etch stop layer is formed directly on said at least one gate spacer, and said at least one source/drain contact via hole stops on an outer surface of said at least one gate spacer after said etching of said exposed portions of said second etch stop layer.