Method for metallization or metallization and interconnection of back contact solar cells

• US 8,766,090 B2
• Filed: 09/28/2012
• Issued: 07/01/2014
• Est. Priority Date: 03/19/2012
• Status: Active Grant

• Current Assignee: Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Original Assignee: Rec Solar Pte. Ltd. (Reliance New Energy Ltd.)
• Inventors: Lyon, Alan Francis, Bentzen, Andreas, Sewell, Richard Hamilton
• Primary Examiner(s): Tran, Long K
• Assistant Examiner(s): KLEIN, JORDAN M
• Application Number:
  US13/631,595
• Publication Number:
  US 20130240023A1
• Time in Patent Office: 641 Days
• Field of Search: 257/E31.13, 257/E31.124, 438/71, 438/96, 438/98, 438/72, 136/256
• US Class Current: 136/256
• CPC Class Codes: H01L 31/022441 Electrode arrangements specially adapted for back-contact solar cells
• CPC Class Codes: H01L 31/0488 Double glass encapsulation, e.g. photovoltaic cells arranged between front and rear glass sheets
• CPC Class Codes: H01L 31/0516 specially adapted for interconnection of back-contact solar cells
• CPC Class Codes: H01L 31/0682 back-junction, i.e. rearside emitter, solar cells, e.g. interdigitated base-emitter regions back-junction cells
• CPC Class Codes: H01L 31/1804 comprising only elements of Group IV of the Periodic Table
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

The present invention relates to cost effective methods for metallization and or metallization and interconnection of high efficiency silicon based back-contacted back-junction solar panels and solar panels thereof having a multiplicity of alternating rectangular emitter- and base regions on the back-side of each cell, each with rectangular metallic electric finger conductor above and running in parallel with the corresponding emitter- and base region, a first insulation layer in-between the wafer and finger conductors, and a second insulation layer in between the finger conductors and cell interconnections.

Claims

1. A method for metallisation and interconnection of a back-contacted back-junction silicon solar wafer, where the solar wafer has:

a layered stratified doped structure at least containing a back-side emitter layer and a base layer below the emitter layer which is formed into a multiplicity of alternating emitter and base regions on the back-side by locally removing rectangular equidistant sections of the emitter layer from one side to the opposite side of the wafer to expose the underlying base layer, and

a front side texturing and surface passivation, and optionally an anti-reflective coating, wherein the method comprises the following process steps in successive order;

depositing a continuous amorphous silicon layer onto the back-side of the wafer covering the multiplicity of alternating emitter and base regions,

depositing a first insulation layer covering the amorphous silicon layer except for one rectilinear opening running in parallel with and located more or less directly above the centre-axis of each of the linear emitter and base regions in an interdigitated multiplicity defining an electric contact access area above each of the linear emitter and base regions of the interdigitated multiplicity of the wafer,

forming the metallisation of the wafer by one of the following;

depositing a continuous metal layer or stack of metal layers covering the first insulation layer including the contact access areas and then patterning the metal layer or stack of metal layers into one finger conductor for each emitter and base regions of the interdigitated multiplicity of the wafer, or

depositing a patterned metal layer or stack of metal layers covering the first insulation layer including the contact access areas defining one finger conductor for each emitter and base regions of the interdigitated multiplicity of the wafer,

depositing a second insulation layer onto the finger conductors with a set of access openings at positions where electric contact with the underlying finger conductor is intended, and

forming a via contact in each access opening in the second insulation layer in electric contact with the finger conductor lying below the access opening, and where

the electric contact with the underlying emitter and base regions of the wafer is obtained by employing Al or an Al—

Si alloy as the first layer of the metallisation being in contact with the amorphous silicon in the access openings in the first insulation layer, and then heating the wafer up to at least 200°

C. to obtain a crystallisation of the amorphous silicon in-between the metallisation and silicon wafer in the access openings.

2. A method according to claim 1, wherein the method comprises the steps of:

employing a multiplicity M=k·

l solar cells, where k and l are an integer from 1 and higher, of the solar cells from claim 1,

laminating the multiplicity of solar cells in a rectangular tessellated-resembling array of k rows and l columns to a module front substrate with their front-side facing the module front substrate,

electrically interconnecting the finger conductors of the solar module by forming a set of ribbons where each ribbon is made to be in electric contact with an intended selection of via contacts in the second insulation layer, and

laminating a back-side cover substrate onto the back-side of the module front substrate including the multiplicity of solar cells.

3. A method according to claim 2, wherein the continuous amorphous silicon layer is formed by loading the module into the amorphous silicon deposition chamber for deposition of 1-50 nm thick layer of α

-Si by chemical vapour deposition (CVD).

4. A method according to claim 3, wherein a continuous layer of SiN_x is deposited onto the continuous amorphous silicon layer by chemical vapour deposition.

5. A method according to claim 1, wherein the insulation layers are made by screen printing a polyimide composition to form a patterned layer of thickness of 1-10 μ

m having linear contact areas with a width in the range from 50-200 μ

m running in parallel and aligned above the centre of each P- and N-type region of the multiplicity of alternating rectangular emitter and base regions and then cured at 180-200°

C.

6. A method according to claim 1, wherein the contact access area are cleaned by plasma ashing in O₂/N₂O, and a hydrofluoric etching after formation of the first insulation layer.

7. A method according to any of the preceding claims claim 1, wherein the continuous metallic layer is deposited by plasma vapour deposition (PVD) until the continuous metallic layer on the back-side of the wafer has a thickness be in one of the following ranges;

from 200 nm to 20 μ

m, from 200 nm to 10 μ

m, from 300 nm to 5 μ

m, from 300 nm to 2 μ

m, from 350 nm to 1 μ

m, or from 350 nm to 800 nm.

8. A method according to claim 7, wherein the continuous metallic layer is a stack of metal layers chosen among the following:

Al/NiCr/Cu, Al/NiCr/SnCu, or AlSi/NiV/SnCu, where the Al or Al-containing alloy is made to be in contact with the amorphous silicon layer.

9. A method according to claim 8, wherein the metal stack also contains an upper contact layer on the opposite side of an adhesion contact layer chosen among one of the following;

Cu, Sn and Ag containing alloys;

a Cu—

Sn—

Ag containing alloy;

a Cu—

Sn alloy;

Sn;

or noble metals such as Au, Ag or Pd.

10. A method according to claim 7, wherein the finger conductors are made by:

DC magnetron sputtering in a multi-chamber tool a continuous Al-layer as a semiconductor contact layer, followed by a continuous layer of Ni_0.8Cr_0.2, and then a continuous layer of Cu using planar targets and Ar as a sputtering gas, and

patterning the deposited continuous metal layers by laser ablation forming linear grooves in the metal layers.

11. A method according to claim 1, wherein the second insulation layer is formed by one of:

applying a patterned adhesive or a printable insulating ink onto the metallic phase (finger conductors) of the wafer,

depositing an un-patterned continuous second insulation layer, and using the subsequent patterned print of conductive material to selectively etch through, penetrate, melt or dissolve the second insulation layer in selected regions,

having the conductive layer acting as a shadow mask to prevent UV curing of the underlying insulator, thus allowing the conductor to penetrate the insulator in the selected areas, or

printing the via conductor pads directly onto the cell metallization, and then flowing a self-levelling insulator layer around the conductor pads to form the second insulating layer by UV curing.

12. A method according to claim 2, wherein the ribbons formed by applying a suitable length of metal strip or band from a spool, stretch and cut the metal strip or band to size, form a strain relief feature and then place the metal strip or band over the second insulating layer with the correct orientation, and then pressing the metal strip or band into the conductive adhesive or solder paste in the access openings.

13. A method according to claim 12, wherein the metal strip has a constant cross-section and is made of solid copper core coated with pure Sn of thickness in one of the following ranges;

from 10 to 300 μ

m, from 20 to 200 μ

m, from 30 to 100 μ

m, from 30 to 60 μ

m, or from 35 to 50 μ

m, and width in one of the following ranges;

from 0.1 to 20 mm, from 0.3 to 15 mm, from 0.5 to 10 mm, from 1 to 8 mm, or from 3 to 6 mm, and where

each ribbon is oriented and located such that is parallel and aligned with either an even or an odd numbered row of the rectangular pattern of m·

n access points of the solar cells, and

is spanning across two solar cells in the same row of the multiplicity of M=k·

l solar cells of the solar module such that;

ribbons aligned with an odd numbered row of the rectangular pattern of m·

n access points of an odd numbered solar cell will connect the emitter type regions of this solar cell with the base type regions of the next solar cell in the row, and

ribbons aligned with an even numbered row of the rectangular pattern of m·

n access points of an odd numbered solar cell will connect the emitter type regions of this solar cell with the base type regions of the previous solar cell in the row,

and if the solar cell is the first solar cell in the row, the ribbons aligned with even numbered rows do only span across this solar cell, and if the solar cell is the last cell in the row, the ribbons aligned with odd numbered rows do only span across this solar cell.

14. A method according to claim 2, wherein the ribbons is formed by applying a suitable length of metal strip or band from a spool, stretch and cut the metal strip or band to size, form a strain relief feature and then place the metal strip or band over the second insulating layer with the correct orientation, and then pressing the metal strip or band into the conductive adhesive or solder paste in the access opening.