Semiconductor devices having bit line insulating capping patterns and multiple conductive patterns thereon

• US 8,766,356 B2
• Filed: 05/23/2013
• Issued: 07/01/2014
• Est. Priority Date: 09/18/2007
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Yong-Il, Kim, Dae-lk
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): Harrison, Monica D
• Application Number:
  US13/900,910
• Publication Number:
  US 20130256793A1
• Time in Patent Office: 404 Days
• Field of Search: 257/298, 257/306, 257/334, 257/E27.084
• US Class Current: 257/334
• CPC Class Codes: H01L 21/82345 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

A semiconductor device capable of reducing a thickness, an electronic product employing the same, and a method of fabricating the same are provided. The method of fabricating a semiconductor device includes preparing a semiconductor substrate having first and second active regions. A first transistor in the first active region includes a first gate pattern and first impurity regions. A second transistor the second active region includes a second gate pattern and second impurity regions. A first conductive pattern is on the first transistor, wherein at least a part of the first conductive pattern is disposed at a same distance from an upper surface of the semiconductor substrate as at least a part of the second gate pattern. The first conductive pattern may be formed on the first transistor while the second transistor is formed.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate having a cell region and a peripheral region;

a cell transistor including a cell gate electrode in a gate trench in the semiconductor substrate and first and second cell source/drain regions in the cell region;

a peripheral transistor including a peripheral gate electrode and first and second peripheral source/drain regions in the peripheral region;

a bit line conductive pattern electrically coupled to the first cell source/drain region;

a bit line insulating capping pattern disposed on the bit line conductive pattern;

a cell contact structure on the second cell source/drain region;

a first conductive pattern on the cell contact structure; and

a second conductive pattern electrically coupled to the bit line conductive pattern and the peripheral transistor,

wherein an upper surface of the first conductive pattern is disposed at substantially a same height above an upper surface of the bit line insulating capping pattern as an upper surface of the second conductive pattern.

2. The semiconductor device of claim 1, wherein the first conductive pattern and the second conductive pattern are in contact with an upper surface of the bit line insulating capping pattern.

3. The semiconductor device of claim 1, further comprising:

a connection structure between the second conductive pattern and the bit line conductive pattern, wherein the connection structure electrically coupled between the bit line conductive pattern and the second conductive pattern through the bit line insulting capping pattern.

4. The semiconductor device of claim 3, further comprising:

an isolation region defining an active region, wherein the connection structure and the isolation region overlap in a direction perpendicular with respect to a surface of the semiconductor substrate.

5. The semiconductor device of claim 1, wherein an upper surface of the bit line conductive pattern is disposed at substantially a same height above an upper surface of the semiconductor substrate as an upper surface of the peripheral gate electrode.

6. The semiconductor device of claim 1, wherein the second conductive pattern is electrically coupled to the first peripheral source/drain region of the peripheral transistor.

7. The semiconductor device of claim 1, further comprising:

an insulating buffer layer on the cell region, wherein the insulating buffer layer is between the bit line conductive pattern and the semiconductor substrate.

8. The semiconductor device of claim 7, further comprising:

a bit line contact structure electrically coupled between the bit line conductive pattern and the first cell source/drain region through the insulating buffer layer.

9. The semiconductor device of claim 1, further comprising:

a cell gate capping pattern on the cell gate electrode, wherein an upper surface of the cell gate capping pattern is higher than an upper surface of the semiconductor substrate.

10. The semiconductor device of claim 1, wherein a portion of the first conductive pattern overlaps the bit line insulating capping pattern.

11. The semiconductor device of claim 1, further comprising:

a peripheral contact structure disposed between the second conductive pattern and the first peripheral source/drain region, wherein the peripheral contact structure is electrically coupled between the second conductive pattern and the first peripheral source/drain region.

12. A semiconductor device comprising:

a semiconductor substrate having a cell region and a peripheral region, the semiconductor substrate including an isolation region defining a cell active region in the cell region and a peripheral active region in the peripheral region;

a cell transistor in the cell region, wherein the cell transistor includes a cell gate electrode in a gate trench in the semiconductor substrate and first and second cell source/drain regions on opposite sides of the gate trench;

a peripheral transistor in the peripheral region, wherein the peripheral transistor includes a peripheral gate electrode on the peripheral active region and first and second peripheral source/drain regions in the peripheral active region adjacent opposite sides of the peripheral gate electrode;

a bit line conductive pattern electrically coupled to the first cell source/drain region;

a bit line insulating capping pattern on the bit line conductive pattern;

a first conductive pattern electrically coupled to the second cell source/drain region; and

a second conductive pattern electrically coupled to the bit line conductive pattern and the first peripheral source/drain region,

wherein portions of the first conductive pattern and the second conductive pattern are disposed on the bit line insulating capping pattern.

13. The semiconductor device of claim 12, further comprising:

a connection structure between the second conductive pattern and the bit line conductive pattern, wherein the connection structure is electrically coupled between the bit line conductive pattern and the second conductive pattern through the bit line insulting capping pattern.

14. The semiconductor device of claim 13, wherein the connection structure and the isolation region overlap in a direction perpendicular with respect to a surface of the semiconductor substrate.

15. The semiconductor device of claim 13, further comprising:

a peripheral contact structure between the second conductive pattern and the first peripheral source/drain region, wherein the peripheral contact structure is electrically coupled between the second conductive pattern and the first peripheral source/drain region.

16. The semiconductor device of claim 12, further comprising:

a cell contact structure between the first conductive pattern and the second cell source/drain region, wherein the cell contact structure is electrically coupled between the first conductive pattern and the second cell source/drain region.

17. The semiconductor device of claim 12, wherein an upper surface of the first conductive pattern is disposed at substantially a same height above an upper surface of the bit line insulating capping pattern as an upper surface of the second conductive pattern.

18. The semiconductor device of claim 12, wherein an upper surface of the bit line conductive pattern is disposed at substantially a same height above an upper surface of the semiconductor substrate as an upper surface of the peripheral gate electrode.

19. The semiconductor device of claim 12, wherein the peripheral gate electrode includes a first peripheral gate electrode pattern and a second peripheral gate electrode pattern,

wherein the bit line conductive pattern and the second peripheral gate electrode pattern comprise a same material and have a same thickness in a direction perpendicular with respect to a surface of the semiconductor substrate.

20. The semiconductor device of claim 12, wherein the first conductive pattern and the second conductive pattern are in contact with the bit line insulating capping pattern.