Circuit-protection devices

• US 8,766,365 B2
• Filed: 02/21/2012
• Issued: 07/01/2014
• Est. Priority Date: 02/21/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Smith, Mike
• Primary Examiner(s): Au, Bac
• Assistant Examiner(s): NGUYEN, SOPHIA T
• Application Number:
  US13/400,678
• Publication Number:
  US 20130214359A1
• Time in Patent Office: 861 Days
• Field of Search: 257/213, 257/288, 257/327, 257/355, 257/357, 257/360, 257/361, 257/363, 257/368, 257/346, 257/347, 257/348, 257/500, 257/504, 257/549, 257/550, 257/553, 257/556, 257/557, 257/55, 257/43, 257/401, 361/91.1, 361/56
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

In an embodiment, a circuit-protection device has first and second circuit-protection units, each comprising first and second nodes. A gate is between the first nodes of first and second circuit-protection units. The first nodes of first and second circuit-protection units are on a common active region.

Claims

1. A circuit-protection device, comprising:

first and second circuit-protection units, each comprising first and second nodes; and

a gate that selectively electrically couples the first node of the first circuit-protection unit to the first node of the second circuit-protection unit in response to a voltage that is selectively applied to a control gate of the gate while a voltage is applied to the first node of the first circuit-protection unit and while a voltage is applied to the first node of the second circuit-protection unit, wherein the voltage that is selectively applied to the control gate of the gate is applied-separately from the voltage applied to the first node of the first circuit-protection unit and separately from the voltage applied to the first node of the second circuit-protection unit;

wherein the first nodes of first and second circuit-protection units are on a common active region of a single conductivity type; and

wherein the gate is configured to electrically isolate the first nodes of first and second circuit-protection units from each other when the first nodes of first and second circuit-protection units are at different voltages and to couple the first nodes of first and second circuit-protection units when the first nodes of first and second circuit-protection units are at about a same voltage that is higher than either of the different voltages.

2. The circuit-protection device of claim 1, wherein the second nodes of first and second circuit-protection units are on separate first and second active regions.

3. The circuit-protection device of claim 2, further comprising an isolation region between the first and second active regions.

4. The circuit-protection device of claim 2, wherein the common active region and the first active region are contiguous, and wherein the common active region and the second active region are contiguous.

5. The circuit-protection device of claim 1, wherein the first and second circuit-protection units are commonly coupled to a control line.

6. The circuit-protection device of claim 1, wherein the first and second circuit-protection units are coupled to different control lines.

7. The circuit-protection device of claim 1, wherein the first and second circuit-protection units and the gate are field-effect transistors.

8. The circuit-protection device of claim 1, wherein the first and second circuit-protection units are field-effect transistors selected from the group consisting of depletion-mode-field-effect transistors, metal-gate-depletion-mode-field-effect transistors, lateral-gate-depletion-mode-field-effect transistors, enhancement-mode-field-effect transistors, metal-gate-enhancement-mode-field-effect transistors, and lateral-gate-enhancement-mode-field-effect transistors.

9. A circuit-protection device, comprising:

first and second circuit-protection units, each comprising first and second nodes; and

a gate coupled to the first nodes of first and second circuit-protection units;

wherein the first nodes of first and second circuit-protection units are on a common active region; and

wherein the gate is configured to electrically isolate the first nodes of first and second circuit-protection units from each other when the first nodes of first and second circuit-protection units are at different voltages and to couple the first nodes of first and second circuit-protection units when the first nodes of first and second circuit-protection units are at about a same voltage that is higher than either of the different voltages.

10. The circuit-protection device of claim 9, wherein the gate being configured to couple the first nodes of first and second circuit-protection units when the first nodes of first and second circuit-protection units are at about a same voltage comprises the gate being configured to be selectively allowed to float.

11. The circuit-protection device of claim 10, wherein the about the same voltage of the first nodes of the first and second circuit-protection units pull up the gate configured to be selectively allowed to float to a voltage sufficient to turn on the gate.

12. A circuit-protection device, comprising:

first and second circuit-protection units, each comprising first and second nodes; and

a gate coupled to the first nodes of first and second circuit-protection units;

wherein the gate is configured to selectively electrically couple the first node of the first circuit-protection unit to the first node of the second circuit-protection unit in response to a voltage that is selectively applied to a control gate of the gate while a voltage is applied to the first node of the first circuit-protection unit and while a voltage is applied to the first node of the second circuit-protection unit, wherein the voltage that is selectively applied to the control gate of the gate is applied separately from the voltage applied to the first node of the first circuit-protection unit and separately from the voltage applied to the first node of the second circuit-protection unit;

wherein the first nodes of first and second circuit-protection units are on a common active region of a single conductivity type;

wherein the first node of the first circuit-protection unit comprises a first source/drain of the gate and the first node of the second circuit-protection unit comprises a second source/drain of the gate; and

wherein the gate is configured to electrically isolate the first nodes of first and second circuit-protection units from each other when the first nodes of first and second circuit-protection units are at different voltages and to couple the first nodes of first and second circuit-protection units when the first nodes of first and second circuit-protection units are at about a same voltage that is higher than either of the different voltages.

13. The circuit-protection device of claim 12, further comprising contacts coupled to the first and second source/drains of the gate.

14. The circuit-protection device of claim 13, wherein the first and second source/drains of the gate comprise regions that are doped to higher conductivity levels than the first and second source/drains, wherein the regions are coupled to the contacts.

15. A circuit-protection device, comprising:

first and second circuit-protection units, each comprising first and second nodes; and

a gate coupled to the first nodes of first and second circuit-protection units;

wherein the first nodes of first and second circuit-protection units are on a common active region; and

wherein the first nodes of first and second circuit-protection units are coupled to data lines of a memory array, and wherein the second nodes of first and second circuit-protection units are coupled to a data cache and/or a data register.

16. The circuit-protection device of claim 15, wherein the gate is configured to electrically isolate the first nodes of first and second circuit-protection units from each other while the memory array is being read from or written to and configured to couple the first nodes of first and second circuit-protection units while the memory array is being erased.

17. A circuit-protection device, comprising:

first and second circuit-protection units, each comprising first and second nodes; and

a gate coupled to the first nodes of first and second circuit-protection units;

wherein the first nodes of first and second circuit-protection units are on a common active region; and

wherein the second nodes of the first and second circuit-protection units are configured to be coupled to low-voltage circuitry and the first nodes of the first and second circuit-protection units are configured to be respectively coupled to circuitries that can be at high voltages or at different low voltages.

18. A memory device having a circuit-protection device, comprising:

first and second transistors, each comprising first and second source/drains; and

a third transistor between the first source/drains of first and second transistors, the third transistor comprising a first source/drain coupled to the first source/drain of the first transistor and a second source/drain coupled to the first source/drain of the second transistor;

wherein the first source/drains of first and second transistors and the first and second source/drains of the third transistor are formed in a common active region and wherein the third transistor is over the common active region; and

wherein the first source/drains of first and second transistors are coupled to data lines of the memory device.

19. The memory device of claim 18, wherein the second source/drains of first and second transistors are coupled to low-voltage circuitry of the memory device.

20. The memory device of claim 18, wherein the second source/drains of first and second transistors are respectively formed in first and second active regions that are separated by an isolation region.

21. The memory device of claim 18, wherein the first and second transistors are commonly coupled to a control line.

22. The memory device of claim 18, wherein the first and second transistors are coupled to different control lines.

23. The memory device of claim 18, further comprising contacts coupled to the first and second source/drains of the first and second transistors.

24. The memory device of claim 23, wherein the first and second source/drains of the first and second transistors comprise regions that are doped to higher conductivity levels than the first and second source/drains of the first and second transistors, wherein the regions are coupled to the contacts.

25. A circuit-protection system, comprising:

first and second circuit-protection devices, each first and second circuit-protection device comprising;

successively adjacent first and second circuit-protection units, each of the first and second circuit-protection units between and coupled to first and second nodes; and

a gate between and coupled to the first nodes coupled to the successively adjacent first and second circuit-protection units of the respective circuit-protection device;

wherein the first nodes are in a common active region of the respective circuit-protection device; and

wherein the second node coupled to the first circuit-protection unit of the second circuit-protection device is between the second nodes coupled to the first and second circuit-protection units of the first circuit-protection device.

26. The circuit-protection system, of claim 25, wherein the first and second circuit-protection units of the first and second circuit-protection devices are lateral-gate-field-effect transistors.

27. The circuit-protection system, of claim 25, further comprising a control line that wraps around the second node coupled to the first circuit-protection unit of the second circuit-protection device that is between the second nodes coupled to the first and second circuit-protection units of the first circuit-protection device and around the second nodes coupled to the first and second circuit-protection units of the first circuit-protection device.

28. The circuit-protection system, of claim 27, wherein the first and second circuit-protection units of the first and second circuit-protection devices are commonly coupled to the control line.

29. The circuit-protection system, of claim 27, wherein the first and second circuit-protection units of the first and second circuit-protection devices each comprise a depletion region coupled to the first and second nodes.

30. The circuit-protection system, of claim 27, wherein the second nodes coupled to the first and second circuit-protection units of the first circuit-protection device are respectively formed in separate active regions that extend from the common active region of the first circuit-protection device, and wherein the second nodes coupled to the first and second circuit-protection units of the second circuit-protection device are respectively formed in separate active regions that extend from the common active region of the second circuit-protection device.

31. The circuit-protection system, of claim 25, wherein the second node coupled to the first circuit-protection unit of the first circuit-protection device is between the second nodes coupled to the first and second circuit-protection units of the second circuit-protection device.