Semiconductor device and manufacturing method thereof

• US 8,766,408 B2
• Filed: 03/07/2007
• Issued: 07/01/2014
• Est. Priority Date: 03/07/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Noma, Takashi, Otsuka, Shigeki, Morita, Yuichi, Okada, Kazuo, Yamada, Hiroshi, Kitagawa, Katsuhiko, Okubo, Noboru, Ishibe, Shinzo, Shinogi, Hiroyuki
• Primary Examiner(s): Graybill, David E
• Application Number:
  US11/714,906
• Publication Number:
  US 20070210437A1
• Time in Patent Office: 2,673 Days
• Field of Search: None
• US Class Current: 257/621
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/68354 used to support diced chips prior to mounting
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A packaged semiconductor device is manufactured by a simplified manufacturing process, and is reduced in cost, in thickness and in size. A device component and a pad electrode connected with the device component are formed on a semiconductor substrate. A supporter is bonded to a top surface of the semiconductor substrate through an adhesive layer. Then, there is formed a protection layer that has an opening at a location corresponding to the pad electrode and covers a side surface and a back surface of the semiconductor substrate. A conductive terminal is formed on the pad electrode at the location corresponding to the opening formed in the protection layer. No wiring layer or conductive terminal is formed on the back surface of the semiconductor substrate. A conductive terminal is formed on a periphery of the supporter outside of and next to the side surface of the semiconductor substrate.

Claims

1. A semiconductor device comprising:

a semiconductor substrate comprising a top surface and a bottom surface;

a supporter, a first surface of which is attached to the top surface of the semiconductor substrate so that an edge portion of the semiconductor substrate recedes from a corresponding edge portion of the supporter;

a connecting electrode disposed on the first surface of the supporter;

a protection layer covering a side surface of the semiconductor substrate and having an opening at the connecting electrode; and

a passivation film covering a portion of the connecting electrode so that the covering portion of the passivation film is disposed between the supporter and the connecting electrode,

wherein no wiring layer is formed on the bottom surface of the semiconductor substrate, and

the passivation film comprises an insulating material and is disposed between the semiconductor substrate and the supporter.

2. The semiconductor device of claim 1, wherein the opening of the protection layer is located over a first principal surface of the connecting electrode, and a second principal surface of the connecting electrode faces the supporter.

3. The semiconductor device of claim 1, further comprising a conductive terminal disposed on the connecting electrode.

4. The semiconductor device of claim 1, wherein the supporter has a through-hole penetrating through the supporter.

5. The semiconductor device of claim 4, wherein the through-hole is formed at a location over the connecting electrode.

6. The semiconductor device of claim 4, further comprising a conductive material disposed in the through-hole of the supporter.

7. The semiconductor device of claim 1, wherein the bottom surface of the semiconductor substrate is not covered with the protection layer.

8. The semiconductor device of claim 1, further comprising an adhesive layer connecting the first surface of the supporter and the top surface of the semiconductor substrate so that a cavity is formed between the semiconductor substrate and the supporter.

10. The semiconductor device of claim 1, further comprising a circuit board on which the semiconductor substrate attached to the supporter is mounted.

11. The semiconductor device of claim 1, wherein the passivation film comprises a silicon nitride film.

9. A stacked semiconductor device comprising:

a first semiconductor device; and

a second semiconductor device stacked on the first semiconductor device, wherein each of the semiconductor devices comprises;

a semiconductor substrate comprising a top surface and a bottom surface,

a supporter, a first surface of which is attached to the top surface of the semiconductor substrate so that an edge portion of the semiconductor substrate recedes from a corresponding edge portion of the supporter,

a connecting electrode disposed on the first surface of the supporter, and

a protection layer covering a side surface of the semiconductor substrate and having an opening at the connecting electrode, and

a passivation film covering a portion of the connecting electrode so that the covering portion of the passivation film is disposed between the supporter and the connecting electrode, the passivation film comprising an insulating material and being disposed between the semiconductor substrate and the supporter,

wherein no wiring layer is formed on the bottom surface of the semiconductor substrate and the supporter has a through-hole penetrating through the supporter, and

the connecting electrode of the first semiconductor device is connected electrically with the connecting electrode of the second semiconductor device.