Method and structure for through-silicon via (TSV) with diffused isolation well

• US 8,766,409 B2
• Filed: 06/24/2011
• Issued: 07/01/2014
• Est. Priority Date: 06/24/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chi-Yeh
• Primary Examiner(s): Maldonado, Julio J
• Assistant Examiner(s): ESKRIDGE, CORY W
• Application Number:
  US13/167,909
• Publication Number:
  US 20120326319A1
• Time in Patent Office: 1,103 Days
• Field of Search: 257/276, 257/621, 257/698, 257/E23.067, 438/667
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76828 thermal treatment
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/6616 Vertical connections, e.g. vias
• CPC Class Codes: H01L 2223/6622 Coaxial feed-throughs in active or passive substrates
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and method for forming the same provide a through silicon via (TSV) surrounded by a dielectric liner. The TSV and dielectric liner are surrounded by a well region formed by thermal diffusion. The well region includes a dopant impurity type opposite the dopant impurity type of the substrate. The well region may be a double-diffused well with an inner portion formed of a first material and with a first concentration and an outer portion formed of a second material with a second concentration. The surrounding well region serves as an isolation well, reducing parasitic capacitance.

Claims

1. An integrated circuit structure comprising:

a substrate of a first dopant impurity type;

a through silicon via (TSV) extending from a top surface of said substrate to a bottom surface of said substrate and filled with a conductive material; and

a well region formed in said substrate surrounding said TSV, said well region comprising a second dopant impurity type and extending from said top surface to said bottom surface and including an inner well portion formed of a first species of said second dopant impurity type and an outer portion formed of a second species of said second dopant impurity type.

2. The integrated circuit structure as in claim 1, wherein said first dopant impurity type comprises P-type and said second dopant impurity type comprises N-type.

3. The integrated circuit structure as in claim 1, wherein said well region extends to sidewalls of said TSV.

4. The integrated circuit structure as in claim 1, wherein said TSV includes sidewalls formed of an oxide liner and said well region surrounds said oxide liner.

5. The integrated circuit structure as in claim 1, wherein said substrate comprises a silicon substrate, said TSV includes a width of about 5-15 microns, said well region includes a width of about 2-20 microns and said conductive material comprises one of copper and tungsten.

12. The integrated circuit structure as in claim 1, wherein said first species of said second dopant impurity type comprises As and said second species of said second dopant impurity type comprises phosphorous.

13. The integrated circuit structure as in claim 1, wherein said first species of said second dopant impurity type comprises phosphorous and said second species of said second dopant impurity type comprises As.

6. An integrated circuit structure comprising:

a substrate of a first dopant impurity type;

a through silicon via (TSV) extending from a top surface of said substrate to an opposed bottom surface of said substrate and filled with a conductive material;

a high concentration region of said first dopant impurity type surrounding said TSV and a well region of a second dopant impurity type surrounding said high concentration region, said high concentration region having a first dopant concentration greater than a second dopant concentration in said well region and each of said well region and said high concentration region extending from said top surface to said opposed bottom surface of said substrate.

7. The integrated circuit structure as in claim 6, wherein said first dopant impurity type comprises N-type, said second dopant impurity type comprises P-type and said high concentration region comprises an N+ region.

8. The integrated circuit structure as in claim 6, wherein said first dopant impurity type comprises one of arsenic and phosphorous, said second dopant impurity comprises boron and said conductive material comprises one of copper and tungsten.

9. The integrated circuit structure as in claim 6, wherein said high concentration region extends to a dielectric layer formed along sidewalls of said TSV.

10. The integrated circuit structure as in claim 6, wherein said TSV includes sidewalls formed of an oxide liner and said high concentration region adjacently surrounds said oxide liner.

11. The integrated circuit structure as in claim 6, further comprising a second TSV extending from said top surface of said substrate to said opposed bottom surface of said substrate, disposed within said well region and surrounded by a further high concentration region of said first dopant impurity type.