Reduction of inrush current due to voltage sags with switch and shunt resistance
First Claim
1. A method for the reduction of inrush current to an electrical load that includes a full-wave rectifier due to short-duration voltage sags on an AC input power voltage, comprising the steps of:
- providing a current-limiting circuit coupled between the AC input power voltage and an electrical load that includes a full-wave rectifier, the current-limiting circuit comprising a parallel arrangement of (a) a switch comprising a parallel arrangement of (i) a semiconductor switch and (ii) a selectively actuatable relay for providing a conductive pathway between the AC input power voltage and the electrical load, and (b) a shunt resistance that limits the current to the electrical load;
providing a zero crossing detector coupled to receive the input power voltage, the zero crossing detector operative to provide a zero crossing signal to the current-limiting circuit in response to detection of a zero crossing in the AC input power voltage;
providing a sag detector coupled to receive the input power voltage, the sag detector operative to provide a signal to the current-limiting circuit in response to detection of a short-duration sag in the AC input power voltage during steady state operation of the electrical load and to provide an altered signal to the current-limiting circuit in response to detection of the end of the sag in the AC input power voltage and return of the AC input power voltage to a nominal level;
applying the AC input power voltage to the electrical load directly through the selectively actuatable relay in the current-limiting circuit;
in response to the signal from the sag detector, actuating the relay in the current-limiting circuit to disconnect the conductive pathway between the AC input power voltage and the electrical load so as to add the shunt resistance to the electrical load;
subsequent to the sag detector detecting that the AC input power voltage has returned to a nominal voltage, receiving a zero crossing signal from the zero crossing detector at the current-limiting circuit; and
in response to the altered signal from the sag detector and the zero crossing signal from the zero crossing detector, reconnecting the AC input power voltage to the electrical load through the semiconductor switch.
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Accused Products
Abstract
Various systems and methods are provided for minimizing an inrush current to a load after a voltage sag in a power voltage. In one embodiment, a method is provided comprising the steps of applying a power voltage to a load, and detecting a sag in the power voltage during steady-state operation of the load. The method includes the steps of adding an impedance to the load upon detection of the sag in the power voltage, and removing the impedance from the load when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage.
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Citations
47 Claims
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1. A method for the reduction of inrush current to an electrical load that includes a full-wave rectifier due to short-duration voltage sags on an AC input power voltage, comprising the steps of:
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providing a current-limiting circuit coupled between the AC input power voltage and an electrical load that includes a full-wave rectifier, the current-limiting circuit comprising a parallel arrangement of (a) a switch comprising a parallel arrangement of (i) a semiconductor switch and (ii) a selectively actuatable relay for providing a conductive pathway between the AC input power voltage and the electrical load, and (b) a shunt resistance that limits the current to the electrical load; providing a zero crossing detector coupled to receive the input power voltage, the zero crossing detector operative to provide a zero crossing signal to the current-limiting circuit in response to detection of a zero crossing in the AC input power voltage; providing a sag detector coupled to receive the input power voltage, the sag detector operative to provide a signal to the current-limiting circuit in response to detection of a short-duration sag in the AC input power voltage during steady state operation of the electrical load and to provide an altered signal to the current-limiting circuit in response to detection of the end of the sag in the AC input power voltage and return of the AC input power voltage to a nominal level; applying the AC input power voltage to the electrical load directly through the selectively actuatable relay in the current-limiting circuit; in response to the signal from the sag detector, actuating the relay in the current-limiting circuit to disconnect the conductive pathway between the AC input power voltage and the electrical load so as to add the shunt resistance to the electrical load; subsequent to the sag detector detecting that the AC input power voltage has returned to a nominal voltage, receiving a zero crossing signal from the zero crossing detector at the current-limiting circuit; and in response to the altered signal from the sag detector and the zero crossing signal from the zero crossing detector, reconnecting the AC input power voltage to the electrical load through the semiconductor switch. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. An apparatus for the reduction of inrush current to an electrical load that includes a full-wave rectifier due to short-duration voltage sags on an AC input power voltage, comprising:
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a zero crossing detector coupled to receive the input power voltage and operative to provide a zero crossing signal in response to detection of a zero crossing in the input power voltage; a sag detector coupled to receive the input power voltage and operative to provide a signal in response to detection of a short-duration sag in the input power voltage applied to the load during a steady-state operation of the load and further operative to provide an altered signal in response to detection of the end of the sag and return of the input power voltage to a nominal level; and a current-limiting circuit coupled between the input power voltage and the electrical load that includes a full-wave rectifier, the current-limiting circuit comprising a parallel arrangement of (a) a first switch, (b) a semiconductor second switch, and (c) an impedance, the current-limiting circuit responsive to the signal from the sag detector to disconnect the input power voltage from the electrical load though the first switch so as to add the impedance to the load, the current-limiting circuit configured to remove the impedance from the load and reconnect the input power voltage to the electrical load through the semiconductor second switch in response to the zero crossing signal and the altered signal from the sag corrector when the power voltage has reached a predefined point in the power voltage cycle after the power voltage has returned to a nominal voltage. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47)
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Specification