Digitally-controlled power amplifier with bandpass filtering/transient waveform control and related digitally-controlled power amplifier cell

• US 8,766,719 B2
• Filed: 05/30/2012
• Issued: 07/01/2014
• Est. Priority Date: 10/17/2011
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Lai, Jie-Wei, Hung, Meng-Hsiung, Staszewski, Robert Bogdan
• Primary Examiner(s): Nguyen, Khanh V
• Application Number:
  US13/484,268
• Publication Number:
  US 20130094611A1
• Time in Patent Office: 762 Days
• Field of Search: 330/127, 330/129, 330/151, 330/297, 375295-297
• US Class Current: 330/151
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03F 3/2178 using more than one switch or switching amplifier in parallel or in series H03F3/2173, H03F3/2175 take precedence
• CPC Class Codes: H03F 3/68 Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602

Abstract

A digitally-controlled power amplifier (DPA) with bandpass filtering includes a radio-frequency (RF) clock input, an amplitude control word (ACW) input, and a plurality of DPA cells. The RF clock input is arranged for receiving an RF clock. The ACW input is arranged for receiving a digital ACW signal. The DPA cells are coupled to the RF clock and the digital ACW signal, wherein at least one of the DPA cells is gradually turned on and off in response to at least one bit of the digital ACW signal.

Claims

1. A digitally-controlled power amplifier (DPA) with bandpass filtering, comprising:

a radio-frequency (RF) clock input, arranged for receiving an RF clock;

an amplitude control word (ACW) input, arranged for receiving a digital ACW signal; and

a plurality of DPA cells, coupled to said RF clock and said digital ACW signal, wherein at least one of said DPA cells is gradually turned on and off in response to at least one bit of said digital ACW signal.

2. The DPA of claim 1, wherein gradual turning on and off is performed through resistive charging of a capacitor.

3. The DPA of claim 1, wherein said at least one of said DPA cells comprises:

a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and

an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprising;

a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and

an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals.

4. The DPA of claim 3, wherein said controller comprises:

a coupling block, comprising a capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and

a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal.

5. The DPA of claim 4, wherein said coupling block further comprises a resistor having a first end coupled to said control block and a second end coupled to said first end of said capacitor.

6. The DPA of claim 4, wherein when said bit of said digital ACW signal is indicative of an ON-to-OFF state transition of said output driver, said control block is operative to delay said ON-to-OFF state transition and pre-charge said capacitor concurrently.

7. The DPA of claim 3, wherein said output driver is a class-D amplifier.

8. A digitally-controlled power amplifier (DPA) with transient waveform control, comprising:

a radio-frequency (RF) clock input, arranged for receiving an RF clock;

an amplitude control word (ACW) input, arranged for receiving a digital ACW signal; and

a plurality of DPA cells, coupled to said RF clock and said digital ACW signal, wherein at least one of said DPA cells is abruptly turned on and off in response to at least one bit of said digital ACW signal.

9. The DPA of claim 8, wherein abrupt turning on is performed through resistive charging of a capacitor.

10. The DPA of claim 8, wherein said at least one of said DPA cells comprises:

a controller, arranged for receiving at least a bit of said digital ACW signal, and generating a plurality of intermediate control signals; and

an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprising;

a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and

an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals.

11. The DPA of claim 10, wherein said controller comprises:

a coupling block, comprising a capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and

a control block, arranged for controlling said intermediate control signals according to at least said bit of said digital ACW signal.

12. The DPA of claim 11, wherein said coupling block further comprises a resistor having a first end coupled to said control block and a second end coupled to said first end of said capacitor.

13. The DPA of claim 11, wherein when said output driver enters an OFF state, said control block is operative to maintain a potential difference of said capacitor.

14. The DPA of claim 10, wherein said output driver is a class-D amplifier.

15. A digitally-controlled power amplifier (DPA) cell, comprising:

a controller, arranged for generating a plurality of intermediate control signals according to a plurality of bias voltages, a radio-frequency (RF) input, and a bit of a digital amplitude control word (ACW) signal; and

an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprising;

a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and

an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals;

wherein said controller refers to said bit of said ACW signal to select at least one of said bias voltages to set at least one of said intermediate control signals.

16. The DPA cell of claim 15, wherein said controller comprises:

a coupling block, comprising a capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and

a control block, arranged for controlling said intermediate control signals according to said bias voltages, said RF input, and said bit of said digital ACW signal.

17. The DPA cell of claim 16, wherein when said bit of said digital ACW signal is indicative of an ON-to-OFF state transition of said output driver, said control block is operative to delay said ON-to-OFF state transition and pre-charge said capacitor concurrently.

18. The DPA cell of claim 16, wherein when said output driver enters an OFF state, said control block is operative to maintain a potential difference of said capacitor.

19. The DPA cell of claim 15, wherein said output driver is a class-D amplifier.

20. A digitally-controlled power amplifier (DPA) cell, comprising:

a controller, arranged for generating a plurality of intermediate control signals according to a plurality of bias voltages, a radio-frequency (RF) input, and a bit of a digital amplitude control word (ACW) signal; and

an output driver, arranged for generating an RF output according to said intermediate control signals, said output driver comprising;

a P-type block, having at least a P-type MOS transistor responsive to a first intermediate control signal of said intermediate control signals; and

an N-type block, having at least an N-type MOS transistor responsive to a second intermediate control signal of said intermediate control signals;

wherein said controller comprises;

a control block, arranged for controlling said intermediate control signals according to said bias voltages, said RF input, and said bit of said digital ACW signal; and

a coupling block, comprising;

a capacitor having a first end coupled to a gate of said P-type MOS transistor and a second end coupled to a gate of said N-type MOS transistor; and

a resistor having a first end coupled to said control block and a second end coupled to said first end of said capacitor.