Graphics system with configurable caches

• US 8,766,995 B2
• Filed: 04/26/2006
• Issued: 07/01/2014
• Est. Priority Date: 04/26/2006
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Yu, Chun, Jiao, Guofang, Du, Yun
• Primary Examiner(s): Crawford, Jacinta M
• Application Number:
  US11/412,678
• Publication Number:
  US 20070252843A1
• Time in Patent Office: 2,988 Days
• Field of Search: 345/506, 345/557, 345/535, 345/501, 345/502, 345/530, 711/118, 711/119, 711/122, 711/151, 711/153, 711/152
• US Class Current: 345/557
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures

Abstract

A graphics system includes a graphics processor and a cache memory system. The graphics processor includes processing units that perform various graphics operations to render graphics images. The cache memory system may include fully configurable caches, partially configurable caches, or a combination of configurable and dedicated caches. The cache memory system may further include a control unit, a crossbar, and an arbiter. The control unit may determine memory utilization by the processing units and assign the configurable caches to the processing units based on memory utilization. The configurable caches may be assigned to achieve good utilization of these caches and to avoid memory access bottleneck. The crossbar couples the processing units to their assigned caches. The arbiter facilitates data exchanges between the caches and a main memory.

Claims

1. An apparatus comprising:

a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images;

a plurality of caches configured to store data for the plurality of processing units;

a crossbar configured to couple the plurality of caches to the plurality of processing units;

a control unit configured to ascertain memory utilization by the plurality of processing units and to pre-assign one or more of the plurality of caches to a selected processing unit of the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics, so that the one or more caches is coupled exclusively to the selected processing unit.

2. The apparatus of claim 1, wherein each of the plurality of caches is assignable to any one of a respective subset of the plurality of processing units.

3. The apparatus of claim 1, wherein the plurality of caches comprise one or more dedicated caches exclusively assigned to the processing unit and at least one configurable cache exclusively assignable to any one of the remaining processing units.

4. The apparatus of claim 3, wherein each configurable cache is assignable to any one of a respective subset of the remaining processing units.

5. The apparatus of claim 3, wherein the remaining processing units comprise a depth test engine and a texture mapping engine.

6. The apparatus of claim 1, wherein the control unit is configured to assign the plurality of caches for each graphics image to be rendered based on memory utilization for a prior graphics image.

7. The apparatus of claim 1, wherein the control unit is configured to ascertain memory utilization based on data requests by the processing units, cache hit/miss statistics, or a combination thereof.

8. The apparatus of claim 1, wherein the control unit is configured to detect changes in memory utilization by the plurality of processing units during rendering of an image and to re-assign the plurality of caches based on the detected changes in memory utilization.

9. The apparatus of claim 1, wherein the control unit is configured to exclusively assign the one or more of the plurality of caches to the processing unit based on memory utilization by a graphics application being executed.

10. The apparatus of claim 1, wherein the crossbar comprises

a plurality of interface units, each interface unit configured to couple an associated processing unit to a set of caches assigned to the processing unit.

11. The apparatus of claim 10, wherein each interface unit comprises a state machine configured to determine whether data requested by the associated processing unit is stored in any one of the set of caches assigned to the processing unit.

12. The apparatus of claim 11, wherein the state machine for each interface unit receives cache hit/miss indicators from the plurality of caches and a control indicating the set of caches assigned to the associated processing unit.

13. The apparatus of claim 11, wherein the state machine for each interface unit is configured to fill one of the set of caches assigned to the associated processing unit when a cache miss occurs.

14. The apparatus of claim 1, wherein the plurality of caches are arranged in a hierarchical structure with at least two levels of caches.

15. The apparatus of claim 14, wherein at least one level in the hierarchical structure has a configurable number of caches.

16. The apparatus of claim 14, wherein at least one level in the hierarchical structure has configurable cache sizes.

17. The apparatus of claim 1, wherein the plurality of caches are arranged in a configurable number of levels in a hierarchical structure.

18. The apparatus of claim 1, wherein the plurality of caches have configurable cache sizes.

19. The apparatus of claim 1, further comprising:

an arbiter coupled to the plurality of caches and configured to facilitate data exchanges between the plurality of caches and a main memory.

20. The apparatus of claim 1, wherein the plurality of processing units comprise a depth test engine and a texture mapping engine.

21. The apparatus of claim 20, wherein the plurality of processing units are arranged in a pipeline, and wherein the depth test engine is located earlier in the pipeline than the texture mapping engine.

22. An integrated circuit comprising:

a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images;

a plurality of caches configured to store data for the plurality of processing units;

a crossbar configured to couple the plurality of caches to the plurality of processing units; and

a control unit configured to ascertain memory utilization by the plurality of processing units and to pre-assign one or more of the plurality of caches to a selected processing unit of the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics, so that the one or more caches is coupled exclusively to the selected processing unit.

23. A wireless device comprising:

a graphics processor comprising a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images; and

a cache memory system comprising

a plurality of caches configured to store data for the plurality of processing units, and

a crossbar configured to couple the plurality of caches to the plurality of processing units; and

a control unit configured to ascertain memory utilization by the plurality of processing units and to pre-assign one or more of the plurality of caches to a selected processing unit of the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics, so that the one or more caches is coupled exclusively to the selected processing unit.

24. The wireless device of claim 23, wherein the cache memory system further comprises

an arbiter coupled to the plurality of caches and configured to facilitate data exchanges between the plurality of caches and a main memory.

25. A method comprising:

determining memory utilization statistics by a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images;

pre-assigning a plurality of caches to a processing unit among the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics by the plurality of processing units; and

exclusively coupling the processing unit to the plurality of caches based on the pre-assigning.

26. The method of claim 25, further comprising:

coupling one or more caches directly to the processing unit among the plurality of processing units.

27. The method of claim 25, wherein the exclusively assigning the plurality of caches comprises

exclusively assigning the plurality of caches to the processing unit for each graphics image to be rendered based on memory utilization for a prior graphics image.

28. An apparatus comprising:

means for determining memory utilization statistics by a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images;

means for pre-assigning a plurality of caches to a processing unit among the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics by the plurality of processing units; and

means for exclusively coupling the processing unit to the plurality of caches.

29. The apparatus of claim 28, further comprising:

means for coupling one or more caches directly to the processing unit among the plurality of processing units.

30. The apparatus of claim 28, wherein the means for exclusively assigning the plurality of caches comprises

means for exclusively assigning the plurality of caches to the processing unit for each graphics image to be rendered based on memory utilization for a prior graphics image.

31. A non-transitory computer-readable memory storing code for causing a computer to configure caches comprising:

code for causing a computer to determine memory utilization statistics by a plurality of processing units arranged in a pipeline, the plurality of processing units configured to perform graphics operations to render graphics images;

code for causing a computer to pre-assign a plurality of caches to a processing unit among the plurality of processing units at the beginning of rendering a frame, image, or batch based on the memory utilization statistics by the plurality of processing units; and

code for causing a computer to exclusively couple the processing unit to the plurality of caches based on the pre-assignment.

32. The non-transitory computer-readable memory of claim 31, further comprising:

code for causing a computer to couple one or more caches directly to the processing unit among the plurality of processing units.

33. The non-transitory computer-readable memory of claim 31, wherein the code for causing a computer to exclusively assign the plurality of caches comprises:

code for causing a computer to exclusively assign the plurality of caches to the processing unit for each graphics image to be rendered based on memory utilization for a prior graphics image.