Unified virtual addressed register file
First Claim
1. A multi-threaded processor comprising:
- a thread scheduler configured to receive multiple threads, each of the threads having one or more thread registers, determine a dynamic size of each of the thread registers of each of the multiple threads, create, in a unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in a unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads, wherein the thread scheduler is further configured to allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads, and store content of each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads;
the unified register file coupled to the thread scheduler;
and a processing unit coupled to the unified register file and configured to retrieve content of the thread registers of each of the multiple threads from the internal addresses in the unified memory space in accordance with the virtual register mapping that maps the one or more allocated virtual registers to internal addresses in the unified memory space.
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Accused Products
Abstract
A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.
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Citations
27 Claims
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1. A multi-threaded processor comprising:
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a thread scheduler configured to receive multiple threads, each of the threads having one or more thread registers, determine a dynamic size of each of the thread registers of each of the multiple threads, create, in a unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in a unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads, wherein the thread scheduler is further configured to allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads, and store content of each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads; the unified register file coupled to the thread scheduler; and a processing unit coupled to the unified register file and configured to retrieve content of the thread registers of each of the multiple threads from the internal addresses in the unified memory space in accordance with the virtual register mapping that maps the one or more allocated virtual registers to internal addresses in the unified memory space. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multi-threaded processor comprising:
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means for receiving multiple threads, each of the threads having one or more thread registers; means for determining a dynamic size of each of the thread registers of each of the multiple threads; means for creating, in a unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in the unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, and wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads; and means for allocating one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads; and means for storing content of each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads. - View Dependent Claims (11, 12, 13, 14)
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15. A method comprising:
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receiving multiple threads at a multi-threaded processor, each of the multiple threads including one or more thread registers; determining a dynamic size of each of the thread registers of each of the multiple threads; creating, in the multi-threaded processor'"'"'s unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in the unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, and wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads; and allocating one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads; and storing content of the each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. A non-transitory machine-readable medium as a memory storage device tangibly storing one or more instructions for processing multiple threads in a multi-threaded processor, which when executed by the multi-threaded processor causes the multi-threaded processor to:
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receive multiple threads, each of the multiple threads including one or more thread registers; determine a dynamic size of each of the thread registers of each of the multiple threads; create, in a multi-threaded processor'"'"'s unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in a unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers, wherein the non-contiguous internal address addresses a portion of the unified memory space, and wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads; allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads; and store content of each of the thread registers of each of the multiple threads at the internal address in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads. - View Dependent Claims (23, 24)
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25. A graphics processor comprising:
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a cache memory for receiving external instructions; a texture engine for storing graphics texture data; a multi-threaded processor coupled to the cache memory and texture engine, the multi-threaded processor configured to receive multiple threads each having one or more thread registers; determine a dynamic size of each of the thread registers of each thread of the multiple threads; create, in the multi-threaded processor'"'"'s unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in the unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers of each thread of the multiple threads, wherein the non-contiguous internal address addresses a portion of the unified memory space, and wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads; allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads; and store content of each of the thread registers of each of the multiple threads at the internal addresses in the unified memory space in accordance with the virtual register mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads. - View Dependent Claims (26)
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27. A wireless communication device comprising:
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a communication interface to wirelessly communicate with other devices; a graphics processor coupled to provide graphics data to the display unit, the graphics processor configured to receive multiple threads each including one or more thread registers; determining a dynamic size of each of the thread registers of each thread of the multiple threads; create a unified register file, a virtual register mapping that defines virtual registers having contiguous addresses and that maps the contiguous virtual registers to internal addresses in the unified register file'"'"'s unified memory space mapped by the virtual registers, wherein the virtual register mapping maps at least one of the contiguous virtual registers to a non-contiguous internal address in the unified memory space in accordance with the determined size of each of the thread registers of each thread of the multiple threads, wherein the non-contiguous internal address addresses a portion of the unified memory space, and wherein a size of the portion of the unified memory space that is addressed by the non-contiguous internal address is based on the determined size of each of the thread registers of each of the multiple threads; allocate one or more of the contiguous virtual registers to the one or more thread registers of each of the multiple threads, a size of at least one of the allocated virtual registers being different from a size of another of the allocated virtual registers, and the size of the at least one of the allocated virtual registers being based on the determined size of each of the thread registers of each of the multiple threads; and store content of each of the thread registers of each of the multiple threads at the internal address in the unified memory space in accordance with the virtual mapping that also indicates which of the one or more allocated virtual registers is allocated to which thread of the multiple threads.
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Specification