Semiconductor device including memory cell array
First Claim
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1. A semiconductor device comprising:
- a memory cell array comprising a memory cell;
a first driver circuit; and
a second driver circuit,wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor,wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region,wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region,wherein the first channel formation region comprises a first semiconductor material,wherein the second channel formation region comprises a second semiconductor material,wherein the first gate electrode, the second drain electrode, and one electrode of the first capacitor are electrically connected to each other,wherein the first driver circuit is electrically connected to the first drain electrode and the second source electrode,wherein the second driver circuit is electrically connected to the other electrode of the first capacitor and the second gate electrode,wherein a second capacitor is provided between the second driver circuit and the memory cell and one electrode of the second capacitor is electrically connected to the second gate electrode,wherein the second capacitor comprises a first conductive layer, an insulating layer over the first conductive layer, a second conductive layer over the insulating layer, a third conductive layer in contact with the second conductive layer, and a fourth conductive layer in contact with the third conductive layer,wherein the first conductive layer comprises the first semiconductor material,wherein the insulating layer is provided in the same layer as a gate insulating layer of the first transistor,wherein the second conductive layer is provided in the same layer as the first gate electrode,wherein the third conductive layer is provided in the same layer as the second source electrode and the second drain electrode, andwherein the fourth conductive layer is provided in the same layer as the second gate electrode.
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Abstract
A semiconductor device in which stored data can be held even when power is not supplied and there is no limitation on the number of writing operations is provided. A semiconductor device is formed using a material which can sufficiently reduce the off-state current of a transistor, such as an oxide semiconductor material that is a wide-gap semiconductor. When a semiconductor material which can sufficiently reduce the off-state current of a transistor is used, the semiconductor device can hold data for a long period. In addition, by providing a capacitor or a noise removal circuit electrically connected to a write word line, a signal such as a short pulse or a noise input to a memory cell can be reduced or removed. Accordingly, a malfunction in which data written into the memory cell is erased when a transistor in the memory cell is instantaneously turned on can be prevented.
129 Citations
19 Claims
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1. A semiconductor device comprising:
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a memory cell array comprising a memory cell; a first driver circuit; and a second driver circuit, wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, wherein the first channel formation region comprises a first semiconductor material, wherein the second channel formation region comprises a second semiconductor material, wherein the first gate electrode, the second drain electrode, and one electrode of the first capacitor are electrically connected to each other, wherein the first driver circuit is electrically connected to the first drain electrode and the second source electrode, wherein the second driver circuit is electrically connected to the other electrode of the first capacitor and the second gate electrode, wherein a second capacitor is provided between the second driver circuit and the memory cell and one electrode of the second capacitor is electrically connected to the second gate electrode, wherein the second capacitor comprises a first conductive layer, an insulating layer over the first conductive layer, a second conductive layer over the insulating layer, a third conductive layer in contact with the second conductive layer, and a fourth conductive layer in contact with the third conductive layer, wherein the first conductive layer comprises the first semiconductor material, wherein the insulating layer is provided in the same layer as a gate insulating layer of the first transistor, wherein the second conductive layer is provided in the same layer as the first gate electrode, wherein the third conductive layer is provided in the same layer as the second source electrode and the second drain electrode, and wherein the fourth conductive layer is provided in the same layer as the second gate electrode. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A semiconductor device comprising:
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a memory cell array comprising a memory cell; a first driver circuit; and a second driver circuit, wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, wherein the first channel formation region comprises a first semiconductor material, wherein the second channel formation region comprises a second semiconductor material, wherein the first gate electrode, the second drain electrode, and one electrode of the first capacitor are electrically connected to each other, wherein the first driver circuit is electrically connected to the first drain electrode and the second source electrode, wherein the second driver circuit is electrically connected to the other electrode of the first capacitor and the second gate electrode, wherein the second driver circuit comprises a noise removal circuit electrically connected to the second gate electrode, wherein the noise removal circuit comprises a first inverter circuit, a second inverter circuit, and a second capacitor, wherein one electrode of the second capacitor is electrically connected to an output terminal of the first inverter circuit and an input terminal of the second inverter circuit, wherein an output terminal of the second inverter circuit is electrically connected to the second gate electrode, wherein the second capacitor comprises a first conductive layer, an insulating layer over the first conductive layer, a second conductive layer over the insulating layer, a third conductive layer in contact with the second conductive layer, and a fourth conductive layer in contact with the third conductive layer, wherein the first conductive layer comprises the first semiconductor material, wherein the insulating layer is provided in the same layer as a gate insulating layer of the first transistor, wherein the second conductive layer is provided in the same layer as the first gate electrode, wherein the third conductive layer is provided in the same layer as the second source electrode and the second drain electrode, and wherein the fourth conductive layer is provided in the same layer as the second gate electrode. - View Dependent Claims (8, 9, 10, 11, 12)
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13. A semiconductor device comprising:
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a memory cell array comprising a memory cell; a first driver circuit; and a second driver circuit, wherein the memory cell comprises a first transistor, a second transistor, and a first capacitor, wherein the first transistor comprises a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, wherein the second transistor comprises a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, wherein the first channel formation region comprises a first semiconductor material, wherein the second channel formation region comprises a second semiconductor material, wherein the first gate electrode, the second drain electrode, and one electrode of the first capacitor are electrically connected to each other, wherein the first driver circuit is electrically connected to the first drain electrode and the second source electrode, wherein the second driver circuit is electrically connected to the other electrode of the first capacitor and the second gate electrode, wherein the second driver circuit comprises a noise removal circuit electrically connected to the second gate electrode, wherein the noise removal circuit comprises an AND circuit and a second capacitor, wherein one electrode of the second capacitor is electrically connected to a first input terminal of the AND circuit, and wherein an output terminal of the AND circuit is electrically connected to the second gate electrode. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification
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Current AssigneeSemiconductor Energy Laboratory Co., Ltd.
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Original AssigneeSemiconductor Energy Laboratory Co., Ltd.
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InventorsMatsuzaki, Takanori, Nagatsuka, Shuhei, Inoue, Hiroki
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Primary Examiner(s)BUI, THA-O H
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Application NumberUS13/230,093Publication NumberTime in Patent Office1,023 DaysField of Search365/129, 365/149, 365/230.05US Class Current365/149CPC Class CodesG11C 11/403 with charge regeneration co...G11C 11/405 with three charge-transfer ...G11C 11/4085 Word line control circuits,...G11C 16/02 electrically programmableG11C 16/0433 comprising cells containing...G11C 16/0483 comprising cells having sev...G11C 16/08 Address circuits; Decoders;...G11C 2211/4016 Memory devices with silicon...G11C 8/08 Word line control circuits,...H10B 99/00 Subject matter not provided...
