Semiconductor memory device and method for inspecting the same

• US 8,767,443 B2
• Filed: 09/19/2011
• Issued: 07/01/2014
• Est. Priority Date: 09/22/2010
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Saito, Toshihiko
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/235,967
• Publication Number:
  US 20120069634A1
• Time in Patent Office: 1,016 Days
• Field of Search: 365/149, 365/210.12, 365/72
• US Class Current: 365/149
• CPC Class Codes: G11C 11/403 with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

When the threshold voltage V_th of the transistor in the memory cell is within the allowable range is determined, a memory cell which does not have sufficient data retention characteristics is eliminated. In order to eliminate such a memory cell, the potential of a gate of the transistor is kept at an appropriate potential V_GM and the potential of a drain of the transistor is set higher than or equal to V_GM. When data is written to the memory cell in this state, the potential of a source of the transistor is expressed as a formula including the threshold voltage V_th, (V_GM−V_th). By comparison between the level of the potential and the level of a reference potential, whether the threshold voltage V_th is within the allowable range can be determined.

Claims

1. A method for inspecting a semiconductor memory device comprising a memory cell including a capacitor and a transistor, one of a source and a drain of the transistor being connected to the capacitor, and the transistor including an oxide semiconductor, the method comprising the steps of:

a first step of turning on the transistor to accumulate electrical charge in the capacitor;

a second step of turning off the transistor and setting the other of the source and the drain of the transistor to a floating state after the first step; and

a third step of applying a voltage to a gate of the transistor and measuring a potential of the other of the source and the drain of the transistor to inspect a threshold voltage of the transistor after the second step.

2. The method for inspecting a semiconductor memory device, according to claim 1, wherein the transistor is an n-channel transistor.

3. The method for inspecting a semiconductor memory device, according to claim 2, wherein the other of the source and the drain of the transistor and the gate of the transistor are connected to a bit line and a word line, respectively.

4. The method for inspecting a semiconductor memory device, according to claim 1,

wherein the memory cell further includes a second transistor, and

wherein the one of the source and the drain of the transistor is connected to a gate of the second transistor.

5. The method for inspecting a semiconductor memory device, according to claim 4, wherein the second transistor includes a single crystal semiconductor.

6. The method for inspecting a semiconductor memory device, according to claim 1, wherein the oxide semiconductor includes at least one of indium, gallium, and zinc.

7. The method for inspecting a semiconductor memory device, according to claim 1, further comprising an auxiliary memory cell,

wherein the auxiliary memory cell is used for the memory cell including the transistor whose threshold voltage is not within a predetermined range.

8. The method for inspecting a semiconductor memory device, according to claim 1, further comprising a sense amplifier,

wherein a first input terminal of the sense amplifier is connected to the other of the source and the drain of the transistor.

9. A method for inspecting a semiconductor memory device comprising a memory cell including a capacitor and a transistor, one of a source and a drain of the transistor being connected to the capacitor, the method comprising the steps of:

turning on the transistor to accumulate electrical charge in the capacitor;

turning off the transistors;

applying a first voltage to a gate of the transistor and measuring a potential of the other of the source and the drain of the transistor to inspect whether a threshold voltage of the transistor is higher than a lower limit of a predetermined range; and

applying a second voltage to the gate of the transistor and measuring the potential of the other of the source and the drain of the transistor to inspect whether the threshold voltage of the transistor is lower than a higher limit of the predetermined range,

wherein the first voltage is lower than the second voltage.

10. The method for inspecting a semiconductor memory device, according to claim 9, wherein the transistor is an n-channel transistor.

11. The method for inspecting a semiconductor memory device, according to claim 10, wherein the other of the source and the drain of the transistor and the gate of the transistor are connected to a bit line and a word line, respectively.

12. The method for inspecting a semiconductor memory device, according to claim 9,

wherein the memory cell further includes a second transistor, and

wherein the one of the source and the drain of the transistor is connected to a gate of the second transistor.

13. The method for inspecting a semiconductor memory device, according to claim 12, wherein the second transistor includes a single crystal semiconductor.

14. The method for inspecting a semiconductor memory device, according to claim 9, wherein the transistor includes an oxide semiconductor.

15. The method for inspecting a semiconductor memory device, according to claim 9, further comprising an auxiliary memory cell,

wherein the auxiliary memory cell is used for the memory cell including the transistor whose threshold voltage is not within the predetermined range.

16. The method for inspecting a semiconductor memory device, according to claim 9, further comprising a sense amplifier,

wherein a first input terminal of the sense amplifier is connected to the other of the source and the drain of the transistor.

17. A semiconductor memory device comprising:

a memory cell comprising a capacitor and a transistor;

a switch connected to a gate of the transistor through a word line; and

a pad operationally connected to the switch,

wherein one of a source and a drain of the transistor is connected to the capacitor,

wherein the transistor includes an oxide semiconductor, and

wherein the switch is configured to transmit at least two potentials to the gate of the transistor through the word line.

18. The semiconductor memory device according to claim 17, wherein the other of the source and the drain of the transistor is connected to a bit line.

19. The semiconductor memory device according to claim 17,

wherein the memory cell further includes a second transistor, and

wherein the one of the source and the drain of the transistor is connected to a gate of the second transistor.

20. The semiconductor memory device according to claim 19, wherein the second transistor includes a single crystal semiconductor.

21. The semiconductor memory device according to claim 17, wherein the oxide semiconductor includes at least one of indium, gallium, and zinc.