Magnetoresistive random access memory

• US 8,767,448 B2
• Filed: 11/05/2012
• Issued: 07/01/2014
• Est. Priority Date: 11/05/2012
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Annunziata, Anthony J.
• Primary Examiner(s): Byrne, Harry W
• Application Number:
  US13/668,869
• Publication Number:
  US 20140126279A1
• Time in Patent Office: 603 Days
• Field of Search: 365/48, 365/55, 365/62, 365/66, 365/74, 365/78, 365 80- 93, 365/100, 365/130, 365/131, 365/148, 365/158, 365171-173, 365/209, 365/213, 365/225.5, 365/230.07, 365/232, 365/243.5, 257/421, 257/E21.665, 438/3, 428810-816, 428817-8251, 428/826, 977933-935
• US Class Current: 365/158
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/1697 Power supply circuits
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices

Abstract

A magnetoresistive random access memory (MRAM) apparatus includes a first conductive line and a second conductive line. A magnetic tunnel junction is in electrical communication with the first conductive line and the second conductive line. The magnetic tunnel junction includes at least one programmable magnetic layer. The MRAM apparatus also includes an insulating layer radially surrounding the magnetic tunnel junction, and the insulating layer has a cavity adjacent to the magnetic tunnel junction.

Claims

1. A magnetoresistive random access memory (MRAM) apparatus, comprising:

a first conductive line;

a second conductive line;

a magnetic tunnel junction in electrical communication with the first conductive line and the second conductive line, the magnetic tunnel junction comprising at least one programmable magnetic layer; and

an insulating layer radially surrounding the magnetic tunnel junction, the insulating layer having a cavity adjacent to the magnetic tunnel junction.

2. The MRAM apparatus of claim 1, wherein the cavity surrounds the magnetic tunnel junction.

3. The MRAM apparatus of claim 1, wherein the insulating layer includes a plurality of cavities adjacent to the magnetic tunnel junction.

4. The MRAM apparatus of claim 1, wherein the insulating layer further includes another cavity adjacent to at least one of the first and second conductive lines.

5. The MRAM apparatus of claim 1, wherein the second conductive line has a resistivity higher than the first conductive line;

and

the second conductive line is electrically connected to a third conductive line having a same resistivity as the first conductive line.

6. The MRAM apparatus of claim 1, wherein the tunnel junction includes a plurality of magnetic tunnel junctions including a first magnetic tunnel junction and a second magnetic tunnel junction,

the first magnetic tunnel junction is connected between the first conductive line and the second conductive line, and

the second magnetic tunnel junction is connected between the second conductive line and a third conductive line.

7. The MRAM apparatus of claim 1, further comprising:

a write line located on an opposite side of the second conductive line from the magnetic tunnel junction.

8. A memory device, comprising:

a magnetoresistive random access memory (MRAM) array comprising a plurality of MRAM cells, each MRAM cell comprising;

a first conductive line;

a second conductive line;

a magnetic tunnel junction in electrical communication with the first conductive line and the second conductive line, the magnetic tunnel junction comprising at least one programmable magnetic layer; and

an insulating layer radially surrounding the magnetic tunnel junction, the insulating layer having a cavity adjacent to the magnetic tunnel junction; and

a processing circuit configured to control a current supplied to the MRAM array to read and write data from and to the MRAM cells of the MRAM array.

9. The memory device of claim 8, wherein the cavity surrounds the magnetic tunnel junction.

10. The memory device of claim 8, wherein the insulating layer includes a plurality of cavities adjacent to the magnetic tunnel junction.

11. The memory device of claim 8, wherein the insulating layer further includes another cavity adjacent to at least one of the first and second conductive lines.