Multi-bit memory with selectable magnetic layer

• US 8,767,456 B2
• Filed: 05/16/2012
• Issued: 07/01/2014
• Est. Priority Date: 10/07/2010
• Status: Expired due to Fees

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Amin, Nurul, Van Ek, Johannes
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/473,448
• Publication Number:
  US 20120224418A1
• Time in Patent Office: 776 Days
• Field of Search: 365/131, 365/158, 365/171, 365/173
• US Class Current: 365/173
• CPC Class Codes: G11B 5/02 Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
• CPC Class Codes: G11B 5/746 Bit Patterned record carriers, wherein each magnetic isolated data island corresponds to a bit
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/5607 using magnetic storage elements

Abstract

An apparatus and associated method for a multi-bit memory capable of being selected with a magnetic layer. Various embodiments of the present invention are generally directed to a first selection layer with a low coercivity that is disposed between first and second storage layers that each have a high coercivity. In response to magnetic saturation of the first selection layer, programming of a logical state to the second storage layer is allowed.

Claims

1. An apparatus comprising:

a first storage layer disposed between first and second selection layers each with low coercivity;

a second storage layer attached to the first selection layer, opposite the first storage layer; and

a third storage layer attached to the second selection layer, opposite the first storage layer, each storage layer configured with high coercivity, where magnetic saturation of both the first and second selection layers allows programming of a logical state to the third storage layer.

2. The apparatus of claim 1, wherein a first source programs the logical state, a second source saturates the first selection layer, and a third source saturates the second selection layer.

3. The apparatus of claim 1, wherein the first and second selection layers are respectively aligned with first and second sources.

4. The apparatus of claim 2, wherein the first storage layer is proximal to the first source, the second storage layer is proximal to the second source, and the second storage layer is distal to the first source so that the selection layer lies between the second storage layer and the first source.

5. The apparatus of claim 1, wherein the first, second, and third storage layers comprise a non-volatile memory cell capable of storing multiple logical states concurrently.

6. The apparatus of claim 5, wherein the first and second selection layers are part of respective first and second common planes that each interconnects multiple memory cells.

7. The apparatus of claim 5, wherein the first and second selection layers are each saturated by current running through the respective first and second common planes.

8. The apparatus of claim 6, wherein each memory cell has a programming source contactingly adjacent a storage layer.

9. The apparatus of claim 1, wherein the first and second selection layers each have selection magnetizations configured perpendicular to logical magnetizations of the first, second, and third storage layers.

10. The apparatus of claim 1, wherein the first storage layer has a first diameter, the second storage layer has a second diameter, and the third storage layer has a third diameter, the first diameter configured to be less than the second and third diameters, the second diameter being less than the third diameter.

11. The apparatus of claim 1, wherein saturation of the first and second selection layers is respectively with a bias magnetic field that is perpendicular to a program field that programs the logical state to the second storage layer.

19. The apparatus of claim 1, wherein the first, second, and third storage layers and the first and second selection layers comprise a multi-bit memory cell.

20. The apparatus of claim 2, wherein the first and second sources are aligned along different first and second planes, the first and second planes being orthogonal.

12. A method comprising:

providing first, second, and third storage layers each configured with high coercivity and respectively separated by first and second selection layers each configured with a low coercivity;

and

programming a logical state to the third storage layer in response to magnetic saturation of both the first and second selection layers.

13. The method of claim 12, wherein the first and second selection layers are magnetically saturated with magnetic bias fields that are removed to induce the first and second selection layers to magnetically shield the second and third storage layers.

14. The method of claim 12, wherein the first storage layer is programmed with the logical state while the first selection layer is not magnetically saturated.

15. The method of claim 12, wherein the logical state of the first, second, and third storage layers can concurrently be read in response to the magnetic saturation of the first and second selection layers.

16. An apparatus comprising:

first and second selection layers each with low coercivity respectively separating first, second, and third storage layers each with a high coercivity, the first storage layer being proximal to a program source; and

first and second selection sources that respectively magnetically saturate the first and second selection layers with magnetic fields, a saturation of the first and second selection layers allowing a program field from the program source to concurrently program a first logical state to the first, second, and third storage layers.

17. The apparatus of claim 16, wherein first storage layer is programmed to a second logical state in the absence of magnetic saturation of the first selection layer.

18. The apparatus of claim 17, wherein the second selection layer is configured with a coercivity that allows concurrent programming of the first logical state to each storage layer upon saturation.