Data storage in analog memory cells across word lines using a non-integer number of bits per cell

• US 8,767,459 B1
• Filed: 07/28/2011
• Issued: 07/01/2014
• Est. Priority Date: 07/31/2010
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Kasorla, Yoav, Sommer, Naftali, Gurgi, Eyal, Anholt, Micha
• Primary Examiner(s): Hur, J. H.
• Application Number:
  US13/192,501
• Time in Patent Office: 1,069 Days
• Field of Search: 365/185.03, 365/185.12, 365/185.24, 365/238.5, 365/184, 365/185.18, 365/185.23, 711/108
• US Class Current: 365/185.03
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 2211/5647 Multilevel memory with bit inversion arrangement
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for data storage includes accepting data for storage in an array of analog memory cells, which are arranged in rows associated with respective word lines. At least a first page of the data is stored in a first row of the array, and at least a second page of the data is stored in a second row of the array, having a different word line from the first row. After storing the first and second pages, a third page of the data is stored jointly in the first and second rows.

Claims

1. A method for data storage, comprising:

accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines;

storing at least a first page of the data in a first row of the array, and at least a second page of the data in a second row of the array, wherein the second row is associated with a different word line from the first row; and

after storing the first and second pages, storing a third page of the data jointly in the first and second rows;

wherein storing the third page includes marking memory cells that suffer from distortion by programming one or more other memory cells with a predetermined programming level, wherein the one or more other memory cells are located in the first row of the array or in the second row of the array.

2. The method according to claim 1, wherein storing the third page comprises selecting respective programming levels at least for one memory cell in the first row and one memory cell in the second row based on a given bit value of the third page.

3. The method according to claim 1, wherein storing the third page comprises storing a given bit of the third page by:

selecting a first programming level for a first memory cell in the first row based on the given bit of the third page and on a corresponding first bit of the first page;

selecting a second programming level for a second memory cell in the second row based on the given bit of the third page and on a corresponding second bit of the second page; and

programming the first and second memory cells to the selected first and second programming levels, respectively.

4. The method according to claim 1, wherein storing the third page comprises storing a given bit of the third page by:

selecting a first programming level for a first memory cell in the first row, and a second programming level for a second memory cell in the second row, based on the given bit of the third page, on a corresponding first bit of the first page and on a corresponding second bit of the second page; and

programming the first and second memory cells to the selected first and second programming levels, respectively.

5. The method according to claim 1, wherein storing the first, second and third pages comprises executing respective, different first, second and third page programming commands.

6. The method according to claim 1, and comprising performing at least one storage operation in a third row, which neighbors the first row or the second row, after storing the first page and before storing the third page.

7. The method according to claim 1, wherein storing the third page comprises programming the memory cells in the first and second row using a number of programming levels that is not an integer power of two.

8. The method according to claim 1, wherein each of the memory cells is programmable to a respective set of programming levels, and wherein storing the third page comprises selecting the programming levels at least for a first memory cell in the first row and a second memory cell in the second row from a partial subset of possible combinations of the programming levels of the first and second memory cells.

9. Apparatus for data storage, comprising:

a memory, which comprises an array of memory cells that are arranged in rows associated with respective word lines; and

storage circuitry, which is configured to accept data for storage in the array, to store at least a first page of the data in a first row of the array, to store at least a second page of the data in a second row of the array, wherein the second row is associated with a different word line from the first row, and, after storing the first and second pages, to store a third page of the data jointly in the first and second rows;

wherein to store the third page of the data, the storage circuitry is further configured to mark memory cells that suffer from distortion by programming one or more memory cells with a predetermined programming level, wherein the one or more other memory cells are located in the first row of the array or in the second row of the array.

10. The apparatus according to claim 9, wherein the storage circuitry is configured to select respective programming levels at least for one memory cell in the first row and one memory cell in the second row based on a given bit value of the third page.

11. The apparatus according to claim 9, wherein the storage circuitry is configured to store a given bit of the third page by:

selecting a first programming level for a first memory cell in the first row based on the given bit of the third page and on a corresponding first bit of the first page;

selecting a second programming level for a second memory cell in the second row based on the given bit of the third page and on a corresponding second bit of the second page; and

programming the first and second memory cells to the selected first and second programming levels, respectively.

12. The apparatus according to claim 9, wherein the storage circuitry is configured to store a given bit of the third page by:

selecting a first programming level for a first memory cell in the first row, and a second programming level for a second memory cell in the second row, based on the given bit of the third page, on a corresponding first bit of the first page and on a corresponding second bit of the second page; and

programming the first and second memory cells to the selected first and second programming levels, respectively.

13. The apparatus according to claim 9, wherein the storage circuitry is configured to store the first, second and third pages by executing respective, different first, second and third page programming commands.

14. The apparatus according to claim 9, wherein the storage circuitry is configured to perform at least one storage operation in a third row, which neighbors the first row or the second row, after storing the first page and before storing the third page.

15. The apparatus according to claim 9, wherein the storage circuitry is configured to store the third page by programming the memory cells in the first and second row using a number of programming levels that is not an integer power of two.

16. The apparatus according to claim 9, wherein each of the memory cells is programmable to a respective set of programming levels, and wherein the storage circuitry is configured to store the third page by selecting the programming levels for at least for a first memory cell in the first row and a second memory cell in the second row from a partial subset of possible combinations of the programming levels of the first and second memory cells.