Non-volatile memory with dynamic multi-mode operation
First Claim
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1. An apparatus comprising:
- a flash memory array;
an input to receive a request that includes a logical address;
a translator configured to map the logical address to a corresponding physical address within the flash memory array; and
circuitry configured to issue i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and
ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision.
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Abstract
A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.
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Citations
15 Claims
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1. An apparatus comprising:
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a flash memory array; an input to receive a request that includes a logical address; a translator configured to map the logical address to a corresponding physical address within the flash memory array; and circuitry configured to issue i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and
ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A system comprising:
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a processing device; and a memory apparatus in communication with the processing device to receive a request that includes a logical address, the memory apparatus including; a flash memory array; a translator configured to map the logical address to a corresponding physical address within the flash memory array; and circuitry configured to issue i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and
ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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Specification