Non-volatile memory with dynamic multi-mode operation

• US 8,767,461 B2
• Filed: 09/10/2013
• Issued: 07/01/2014
• Est. Priority Date: 02/16/2007
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Kim, Jin-Ki
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US14/022,805
• Publication Number:
  US 20140010019A1
• Time in Patent Office: 294 Days
• Field of Search: 365/185.01, 365/185.03, 365/185.11, 365/185.12, 365/185.23, 365/185.33, 365/168
• US Class Current: 365/185.03
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7204 Capacity control, e.g. partitioning, end-of-life degradation
• CPC Class Codes: G06F 2212/7206 Reconfiguration of flash memory system
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 2211/5646 Multilevel memory with flag bits, e.g. for showing that a "first page" of a word line is programmed but not a "second page"

Abstract

A method and system for extending the life span of a flash memory device. The flash memory device is dynamically configurable to store data in the single bit per cell (SBC) storage mode or the multiple bit per cell (MBC) mode. In the MBC storage mode, the cell can have one of multiple possible states, where each state is defined by respective threshold voltage ranges. In the SBC mode, the cell can have states with threshold voltages corresponding to states of the MBC storage mode which are non-adjacent to each other to improve reliability characteristics of the cell.

Claims

1. An apparatus comprising:

a flash memory array;

an input to receive a request that includes a logical address;

a translator configured to map the logical address to a corresponding physical address within the flash memory array; and

circuitry configured to issue i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and

ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision.

2. The apparatus of claim 1 wherein the first and second subdivisions each include a block, the block having a predetermined number of pages.

3. The apparatus of claim 1 wherein at least one of the first and second subdivisions is a page of a memory block.

4. The apparatus of claim 1 wherein the first type of program command is a Single Bit per Cell (SBC) storage mode specific command.

5. The apparatus of claim 1 wherein the flash memory array is a NAND flash memory array.

6. The apparatus of claim 1 wherein the circuitry comprises a command decoder.

7. A system comprising:

a processing device; and

a memory apparatus in communication with the processing device to receive a request that includes a logical address, the memory apparatus including;

a flash memory array;

a translator configured to map the logical address to a corresponding physical address within the flash memory array; and

circuitry configured to issue i) a first type of program command when the physical address is within a first subdivision of the flash memory array; and

ii) a second different type of program command when the physical address is within a second subdivision of the flash memory array, the first subdivision being different than the second subdivision.

8. The system of claim 7 wherein the first and second subdivisions each include a block, the block having a predetermined number of pages.

9. The system of claim 7 wherein at least one of the first and second subdivisions is a page of a memory block.

10. The system of claim 7 wherein the first type of program command is a Single Bit per Cell (SBC) storage mode specific command.

11. The system of claim 7 wherein the flash memory array is a NAND flash memory array.

12. The system of claim 7 wherein the circuitry comprises a command decoder.

13. The system of claim 7 wherein the processing device comprises a microcontroller.

14. The system of claim 7 wherein the processing device comprises a microprocessor.

15. The system of claim 7 wherein the processing device comprises a computer system.