Non-volatile dynamic random access memory system with non-delay-lock-loop mechanism and method of operation thereof

• US 8,767,463 B2
• Filed: 08/11/2011
• Issued: 07/01/2014
• Est. Priority Date: 08/11/2011
• Status: Active Grant

• Current Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Original Assignee: SMART Modular Technologies Incorporated (Smart Global Holdings Incorporated)
• Inventors: Amidi, Mike H., Marino, Kelvin
• Primary Examiner(s): Bui, Tha-O H
• Application Number:
  US13/207,503
• Publication Number:
  US 20130039128A1
• Time in Patent Office: 1,055 Days
• Field of Search: 365/51, 365/189.02, 365/194, 365/233.1, 365/233.13
• US Class Current: 365/185.08
• CPC Class Codes: G11C 14/0009 in which the volatile element is a DRAM cell

Abstract

A method of operation of a non-volatile dynamic random access memory system including: accessing a dynamic random access memory; managing a delay-locked-loop control in the dynamic random access memory; sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including: selecting a back-up interface through a first multiplexer and a second multiplexer, asserting an on-board termination, and accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including: selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof, disabling the on-board termination, and accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.

Claims

1. A method of operation of a non-volatile dynamic random access memory system comprising:

accessing a dynamic random access memory;

managing a delay-locked-loop control in the dynamic random access memory;

sourcing timing inputs to the dynamic random access memory by a control logic unit with the delay-locked-loop control disabled including;

selecting a back-up interface through a first multiplexer and a second multiplexer,

asserting an on-board termination, and

accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and

enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including;

selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof,

disabling the on-board termination, and

accessing the data in the dynamic random access memory by the memory control interface at a delay-locked-loop frequency.

2. The method as claimed in claim 1 further comprising accessing an interface status bus by the control logic unit.

3. The method as claimed in claim 1 further comprising transferring data from the dynamic random access memory to a non-volatile memory by the control logic unit.

4. The method as claimed in claim 1 further comprising monitoring a power good decision block for managing the delay-locked-loop control.

5. The method as claimed in claim 1 further comprising enabling a first rank memory device to the memory control interface by the control logic unit.

6. A method of operation of a non-volatile dynamic random access memory system comprising:

accessing a dynamic random access memory having a delay-locked-loop;

managing a delay-locked-loop control for controlling the delay-locked-loop;

sourcing timing inputs to the dynamic random access memory by a control logic unit, with the delay-locked-loop control disabled including;

selecting a back-up interface through a first multiplexer and a second multiplexer,

asserting an on-board termination, and

accessing data in the dynamic random access memory by the control logic unit at a lower frequency; and

enabling a memory control interface by the control logic unit, with the delay-locked-loop control enabled including;

selecting a host interface through the first multiplexer, the second multiplexer, or a combination thereof,

disabling the on-board termination for the first multiplexer, the second multiplexer, or a combination thereof, and

accessing the data in the dynamic random access memory by the memory control interface at a delay locked loop frequency through the first multiplexer, the second multiplexer, or a combination thereof.

7. The method as claimed in claim 6 further comprising accessing an interface status bus by the control logic unit including enabling a first rank memory device.

8. The method as claimed in claim 6 further comprising transferring data from the dynamic random access memory to a non-volatile memory by the control logic unit including sampling a monitor system power block for capturing the state of the system power.

9. The method as claimed in claim 6 further comprising monitoring a power good decision block for managing the delay-locked-loop control including enabling the delay-locked-loop of a first rank memory device while the delay-locked-loop of subsequent rank of memory devices is disabled.

10. The method as claimed in claim 6 further comprising enabling a first rank memory device to the memory control interface by the control logic unit including accessing a subsequent rank of memory devices for transferring data from a non-volatile memory.

11. A non-volatile dynamic random access memory system comprising:

a dynamic random access memory;

a delay-locked-loop control in the dynamic random access memory;

a control logic unit coupled to the dynamic random access memory through timing inputs with the delay-locked-loop control disabled including;

a back-up interface selected through a first multiplexer and a second multiplexer, and

a non-volatile memory coupled to the control logic unit for storing data from the dynamic random access memory by the control logic unit at a lower frequency; and

a memory control interface enabled by the control logic unit, with the delay-locked-loop control enabled including;

a host interface coupled to the first multiplexer, the second multiplexer, and the memory control interface, and

a control line between the first multiplexer and the control logic unit.

12. The system as claimed in claim 11 further comprising an interface status bus coupled to the control logic unit includes the memory control interface blocked.

13. The system as claimed in claim 11 further comprising an on-board termination, coupled to the first multiplexer, controlled by the control logic unit.

14. The system as claimed in claim 11 further comprising a subsequent on-board termination, coupled to the second multiplexer, controlled by the control logic unit.

15. The system as claimed in claim 11 further comprising a first rank memory device coupled to the first multiplexer for controlling a memory bus by the control logic unit or the memory control interface.

16. The system as claimed in claim 11 further comprising a delay-locked-loop in the dynamic random access memory controlled by the control logic unit.

17. The system as claimed in claim 16 further comprising an interface status bus coupled between the control logic unit and the memory control interface for blocking access through the memory control interface.

18. The system as claimed in claim 16 further comprising an on-board termination, coupled to the first multiplexer, with a control line controlled by the control logic unit.

19. The system as claimed in claim 16 further comprising a subsequent on-board termination, coupled to the second multiplexer, with a back-up control line controlled by the control logic unit.

20. The system as claimed in claim 16 further comprising a first rank memory device coupled to the first multiplexer and subsequent rank memory devices coupled to the second multiplexer includes the non-volatile memory accessed for restoring a data to the first rank memory device and the subsequent rank memory devices by the control logic unit.