Physical transceiver gearbox

• US 8,767,762 B2
• Filed: 06/22/2012
• Issued: 07/01/2014
• Est. Priority Date: 06/22/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Wentroble, Mark E., Koh, T-Pinn R.
• Primary Examiner(s): Skripnikov, Alex
• Application Number:
  US13/531,369
• Publication Number:
  US 20130343439A1
• Time in Patent Office: 739 Days
• Field of Search: None
• US Class Current: 370/419
• CPC Class Codes: H03M 13/175 Error trapping or Fire codes

Abstract

An apparatus is provided. Physical medium dependent (PMD) sublayer logic is configured to communicate with a communications medium. Physical medium attachment (PMA) sublayer logic is coupled to the PMD logic. Forward error correction (FEC) sublayer logic is coupled to the PMA sublayer logic, and physical coding (PCS) sublayer logic is configured to communicate with an interface. A transmit path is coupled to the transmit data in a second clock domain to the FEC sublayer logic. A first read pointer circuit is coupled to transmit path. A write pointer circuit is coupled to the transmit path. A receive path is coupled to receive data in the second clock domain from the FEC sublayer logic. A second read pointer circuit is coupled to the receive path, where the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

Claims

1. An apparatus comprising:

physical medium dependent (PMD) sublayer logic that is configured to communicate with a communications medium;

physical medium attachment (PMA) sublayer logic that is coupled to the PMD logic;

forward error correction (FEC) sublayer logic that is coupled to the PMA sublayer logic; and

physical coding (PCS) sublayer logic that is configured to communicate with an interface, wherein the PCS sublayer logic includes gearbox circuitry having;

a transmit path that is configured to receive data in a first clock domain and that is coupled to transmit data in a second clock domain to the FEC sublayer logic;

a first read pointer circuit that is coupled to the transmit path;

a write pointer circuit that is coupled to the transmit path;

a receive path that is coupled to receive data in the second clock domain from the FEC sublayer logic and that is configured to output data in the first clock domain; and

a second read pointer circuit that is coupled to the receive path, wherein the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

2. The apparatus of claim 1, wherein the PCS sublayer logic further comprises:

a PCS transmitter that is configured to communicate with the interface and that is coupled to the FEC sublayer logic; and

a PCS receiver that is configured to communicate with the interface and that is coupled to the FEC sublayer logic.

3. The apparatus of claim 2, wherein the gearbox circuitry further comprises a transmit gear box that includes the transmit path, the first read pointer circuit, and the write pointer circuit and a receive gearbox that includes the receive path and the second read pointer circuit.

4. The apparatus of claim 3, wherein the PCS transmitter further comprises:

an encoder that is configured to communicate with the interface; and

a scrambler that is coupled to the encoder and the transmit gearbox.

5. The apparatus of claim 4, wherein the PCS receiver further comprises:

a decoder that is configured to communicate with the interface; and

a descrambler that is coupled to the encoder and the receive gearbox.

6. The apparatus of claim 5, wherein each of the first read pointer circuits, second read pointer circuits, and the write pointer circuits further comprises:

a first flip-flop that is configured to receive a first clock signal in the first clock domain;

a second flip-flop that is coupled to the first flip-flop and that is configured to receive a second clock signal in the second clock domain;

a logic gate that is coupled to the first and second flip-flops;

a multiplexer that is coupled to the logic gate;

a register that is coupled to the multiplexer; and

an incrementer that is coupled to the register and the multiplexer.

7. The apparatus of claim 6, wherein the multiplexer further comprises a first multiplexer, and wherein the transmit gearbox further comprises:

a write matrix that is coupled to a scrambler;

a second multiplexer that is coupled to the write matrix and the write pointer circuit;

a first buffer that is coupled to the first multiplexer;

a third multiplexer that is coupled to the buffer and the first read pointer circuit; and

a second buffer that is coupled to the third multiplexer.

8. The apparatus of claim 7, wherein the receive gearbox further comprises:

a third buffer that is coupled to the FEC sublayer logic; and

a fourth multiplexer that is coupled to the third buffer, the second read pointer circuit, and the descrambler.

9. The apparatus of claim 8, wherein the first and second flip-flops further comprises first and second D flip-flops, and wherein the logic gate further comprises an XOR gate.

10. An apparatus comprising:

a communications medium;

a plurality of network interfaces, wherein each network interface includes;

a media access control (MAC) circuit;

a media independent interface (MII) that is coupled to the MAC circuit; and

a physical transceiver (PHY) having;

PMD sublayer logic that is coupled to the MII;

PMA sublayer logic that is coupled to the PMD logic;

FEC sublayer logic that is coupled to the PMA sublayer logic; and

PCS sublayer logic that is configured to communicate with an interface, wherein the PCS sublayer logic includes gearbox circuitry having;

a transmit path that is configured to receive data in a first clock domain and that is coupled to transmit data in a second clock domain to the FEC sublayer logic;

a first read pointer circuit that is coupled to the transmit path;

a write pointer circuit that is coupled to the transmit path;

a receive path that is coupled to receive data in the second clock domain from the FEC sublayer logic and that is configured to output data in the first clock domain; and

a second read pointer circuit that is coupled to the receive path, wherein the first read pointer circuit, the second read pointer circuit, and the write pointer circuits are each configured to detect gaps between the first and second clock domains.

11. The apparatus of claim 10, wherein the PCS sublayer logic further comprises:

a PCS transmitter that is coupled to the FEC sublayer logic and the MII; and

a PCS receiver that is coupled to the FEC sublayer logic and the MII.

12. The apparatus of claim 11, wherein the gearbox circuitry further comprises a transmit gear box that includes the transmit path, the first read pointer circuit, and the write pointer circuit and a receive gearbox that includes the receive path and the second read pointer circuit.

13. The apparatus of claim 12, wherein the PCS transmitter further comprises:

an encoder that is configured to communicate with the interface; and

a scrambler that is coupled to the encoder and the transmit gearbox.

14. The apparatus of claim 13, wherein the PCS receiver further comprises:

a decoder that is configured to communicate with the interface; and

a descrambler that is coupled to the encoder and the receive gearbox.

15. The apparatus of claim 14, wherein each of the first read pointer circuits, second read pointer circuits, and the write pointer circuits further comprises:

a first flip-flop that is configured to receive a first clock signal in the first clock domain;

a second flip-flop that is coupled to the first flip-flop and that is configured to receive a second clock signal in the second clock domain;

a logic gate that is coupled to the first and second flip-flops;

a multiplexer that is coupled to the logic gate;

a register that is coupled to the multiplexer; and

an incrementer that is coupled to the register and the multiplexer.

16. The apparatus of claim 15, wherein the multiplexer further comprises a first multiplexer, and wherein the transmit gearbox further comprises:

a write matrix that is coupled to a scrambler;

a second multiplexer that is coupled to the write matrix and the write pointer circuit;

a first buffer that is coupled to the first multiplexer;

a third multiplexer that is coupled to the buffer and the first read pointer circuit; and

a second buffer that is coupled to the third multiplexer.

17. The apparatus of claim 16, wherein the receive gearbox further comprises:

a third buffer that is coupled to the FEC sublayer logic; and

a fourth multiplexer that is coupled to the third buffer, the second read pointer circuit, and the descrambler.

18. The apparatus of claim 17, wherein the first and second flip-flops further comprises first and second D flip-flops, and wherein the logic gate further comprises an XOR gate.

19. The apparatus of claim 18, wherein the apparatus further comprises a plurality of hosts, wherein each host is coupled to at least one of the MAC circuits.