Method and system for reconfigurable channel coding

• US 8,767,804 B2
• Filed: 08/20/2012
• Issued: 07/01/2014
• Est. Priority Date: 05/08/2001
• Status: Expired due to Term

• Current Assignee: Cornami, Inc.
• Original Assignee: QST Holdings LLC
• Inventors: Scheuermann, W. James
• Primary Examiner(s): Vo, Don N
• Application Number:
  US13/589,656
• Publication Number:
  US 20130044792A1
• Time in Patent Office: 680 Days
• Field of Search: 375/219, 375/222, 375/223, 455/418, 455/552
• US Class Current: 375/219
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04L 1/0043 Realisations of complexity reduction techniques, e.g. use of look-up tables
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 Convolutional codes
• CPC Class Codes: H04L 65/75 Media network packet handling
• CPC Class Codes: H04L 65/756 adapting media to device capabilities

Abstract

Aspects of a reconfigurable system for providing channel coding in a wireless communication device are described. The aspects include a plurality of computation elements for performing channel coding operations and memory for storing programs to direct each of the plurality of computation elements. A controller controls the plurality of computation elements and stored programs to achieve channel coding operations in accordance with a plurality of wireless communication standards. The plurality of computation elements include a data reordering element, a linear feedback shift register (LFSR) element, a convolutional encoder element, and a Viterbi decoder element.

Claims

1. A wireless communications integrated circuit for providing channel coding in a wireless communication device comprising:

a plurality of computation elements for performing channel coding operations;

an interconnection network coupled to the plurality of computation elements, the interconnection network including switchable interconnections between the computation elements, the interconnection network transmitting configuration information and data between the computation elements; and

a controller for changing the interconnections of the interconnection network to reconfigurably control the plurality of computation elements based on configuration information to achieve channel coding operations in accordance with a plurality of wireless communication standards.

2. The wireless communications integrated circuit of claim 1 further comprising a memory for storing programs, and wherein the stored programs comprise instructions for reconfiguring the plurality of computational elements for the channel coding operations.

3. The wireless communications integrated circuit of claim 1 wherein each of the plurality of computation elements comprises memory for storing programs, and wherein the stored programs comprise instructions for executing commands for the channel coding operations.

4. The wireless communications integrated circuit of claim 1 wherein the plurality of computation elements comprises a plurality of polynomial generators that further comprise a configuration register, an AND logic means, and an exclusive-OR logic means.

5. The wireless communications integrated circuit of claim 1 wherein the plurality of computation elements further comprises a Viterbi decoder element.

6. The wireless communications integrated circuit of claim 5 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.

7. The wireless communications integrated circuit of claim 1, wherein the controller is one of the group of a RISC, a CISC, a CPU, a microprocessor, a software state machine, a hardware state machine, and a DSP.

8. A method for providing channel coding in a wireless communication device comprising:

selecting one of a plurality of wireless communication standards; and

reconfigurably controlling a plurality of computation elements on an integrated circuit by changing interconnections of an interconnection network between the computation elements to achieve channel coding operations in accordance with the selected wireless communication standard via transmission of configuration information over the interconnection network;

operating the channel coding operation in accordance with the selected wireless communication standard using data transmitted over the interconnection network between the computation elements.

9. The method of claim 8, further comprising selecting a mode of the selected one of the plurality of wireless communication standards.

10. The method of claim 8, wherein selecting one of the plurality of wireless communication standards comprises:

receiving a signal associated with one of the plurality of wireless communication standards; and

identifying the one of the plurality of wireless communication standards based on the coding of the signal.

11. The method of claim 8, wherein the plurality of computation elements comprises a data reordering element, a linear feedback shift register (LFSR) element, and a convolutional encoder, wherein the convolutional encoder further comprises a coupled configuration of an input shift register, a delay register, a plurality of polynomial generators, and an output shift register.

12. The method of claim 8, further comprising mapping the bit-oriented operations to the byte-oriented memory and plurality of computation elements.

13. A wireless communications integrated circuit for providing channel coding in a wireless communication device comprising:

a plurality of computation elements for performing channel coding operations;

an interconnection network coupled to the plurality of computation elements, the interconnection including switchable interconnections between the computation elements; and

a controller for changing the interconnections of the interconnection network in accordance with configuration information transmitted through the interconnection network to reconfigurably control the plurality of computation elements to achieve channel coding operations on data transmitted through the interconnection network, the operations in accordance with a plurality of wireless communication modes within a wireless communication standard.

14. The wireless communications integrated circuit of claim 13 further comprising a memory for storing programs, and wherein the stored programs comprise instructions for reconfiguring the plurality of computational elements for the channel coding operations.

15. The wireless communications integrated circuit of claim 13 wherein each of the plurality of computation elements comprises a memory for storing programs, and wherein the stored programs comprise instructions for executing commands for the channel coding operations.

16. The wireless communications integrated circuit of claim 13 wherein the plurality of computation elements comprises a plurality of polynomial generators.

17. The wireless communications integrated circuit of claim 13 wherein the plurality of computation elements comprises a Viterbi decoder element.

18. The wireless communications integrated circuit of claim 17 wherein the Viterbi decoder element further comprises a coupled configuration of a counter, a codeword and punctures look-up table, a register, recode logic, an address generator, path metrics memory, state registers, plus/minus adjusters, adders, a selector, and a comparator.

19. The wireless communications integrated circuit of claim 13, wherein the controller is one of the group of a RISC, a CISC, a CPU, a microprocessor, a software state machine, a hardware state machine, and a DSP.