Interrupt latency reduction
First Claim
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1. An integrated circuit comprising:
- a processor configured to execute instructions;
an interrupt controller coupled to the processor, the interrupt controller configured to transmit an interrupt request to the processor; and
a clock system coupled to the processor, the clock system configured to increase a clock signal frequency received by the processor in response to the interrupt request after the interrupt controller receives a notification signal from the processor and before the processor executes further instructions, wherein the further instructions comprise execution of the interrupt request.
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Abstract
A method in accordance with one embodiment of the invention can include detecting an interrupt request during execution of an instruction by a processor of an integrated circuit. Additionally, a clock signal frequency can be changed that is received by the processor. An interrupt service routine can be executed that corresponds to the interrupt request.
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Citations
18 Claims
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1. An integrated circuit comprising:
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a processor configured to execute instructions; an interrupt controller coupled to the processor, the interrupt controller configured to transmit an interrupt request to the processor; and a clock system coupled to the processor, the clock system configured to increase a clock signal frequency received by the processor in response to the interrupt request after the interrupt controller receives a notification signal from the processor and before the processor executes further instructions, wherein the further instructions comprise execution of the interrupt request. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. An integrated circuit comprising:
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a processor configured to execute instructions; a clock system coupled to supply clock signals to the processor and to at least one system of the integrated circuit; and an interrupt controller coupled to the processor and the clock system, the interrupt controller configured to transmit an interrupt request to the processor and to the clock system;
the clock system configured to respond to the interrupt request by increasing a clock signal frequency supplied to the processor after the interrupt controller receives a notification signal from the processor and before the processor executes further instructions, wherein the further instructions comprise storing a program counter and a status flag associated with an instruction of a program currently being executed by the processor, and by subsequently decreasing the clock signal frequency supplied to the processor before the processor executes a next instruction of the program. - View Dependent Claims (10, 11, 12)
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13. An integrated circuit comprising:
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a processor configured to execute instructions; a clock system coupled to supply clock signals to the processor and to at least one digital system of the integrated circuit; an interrupt controller coupled to the processor and to the clock system, the interrupt controller configured to transmit an interrupt request to the processor and to the clock system; the clock system configured to respond to the interrupt request by increasing from a first frequency to a higher frequency, a clock signal frequency supplied to the processor after the interrupt controller receives a notification signal from the processor and before the processor executes further instructions, wherein the further instructions comprise execution of the interrupt request;
by decreasing to the first frequency the clock signal frequency supplied to the processor when the execution of the interrupt request has completed; and
by maintaining unchanged a frequency of clock signals to said at least one digital system. - View Dependent Claims (14, 15, 16, 17, 18)
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Specification