External memory controller node
First Claim
Patent Images
1. A computing machine comprising:
- a memory;
a first computational node embodied in a first integrated circuit and a second computational node embodied in a second integrated circuit, each computational node configured to make requests for memory accesses for selected data to the memory via a stride parameter, the first and second computational nodes being heterogeneous from each other;
a network coupled to the memory and the first and second computational nodes; and
a memory controller node coupled to the memory and the network and configured to receive requests for memory accesses by the computational nodes to the memory for selected data stored in the memory and generate row and column memory addresses corresponding to stored data and use the stride parameter to access the requested data selected from some of the data stored at the row and column memory addresses from the requests.
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Abstract
A memory controller to provide memory access services in an adaptive computing engine is provided. The controller comprises: a network interface configured to receive a memory request from a programmable network; and a memory interface configured to access a memory to fulfill the memory request from the programmable network, wherein the memory interface receives and provides data for the memory request to the network interface, the network interface configured to send data to and receive data from the programmable network.
416 Citations
20 Claims
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1. A computing machine comprising:
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a memory; a first computational node embodied in a first integrated circuit and a second computational node embodied in a second integrated circuit, each computational node configured to make requests for memory accesses for selected data to the memory via a stride parameter, the first and second computational nodes being heterogeneous from each other; a network coupled to the memory and the first and second computational nodes; and a memory controller node coupled to the memory and the network and configured to receive requests for memory accesses by the computational nodes to the memory for selected data stored in the memory and generate row and column memory addresses corresponding to stored data and use the stride parameter to access the requested data selected from some of the data stored at the row and column memory addresses from the requests. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A computing machine comprising:
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a memory; a plurality of computational nodes embodied in an integrated circuit and each configured to make requests for memory accesses to the memory and setting control and status parameters, at least two of the computational nodes being heterogeneous from each other; a network coupled to the plurality of computational nodes, the network embodied in the integrated circuit; and a memory controller node coupled to the network and the memory, the memory controller node configured to receive requests for memory accesses by the computational nodes to the memory and generate memory addresses from the requests. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification