Memory modules and devices supporting configurable data widths

• US 8,769,234 B2
• Filed: 02/27/2013
• Issued: 07/01/2014
• Est. Priority Date: 02/28/2001
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Stark, Donald C., Ware, Frederick A., Tsern, Ely K., Hampel, Craig E.
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US13/778,534
• Publication Number:
  US 20130286706A1
• Time in Patent Office: 489 Days
• Field of Search: 711/5, 711/115, 711/170
• US Class Current: 711/170
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1087 : Data input latches
• CPC Class Codes: G11C 8/06 : Address interface arrangements, e.g. address buffers
• CPC Class Codes: H05K 1/117 : Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 1/14 : Structural association of two or more printed circuits providing electric connection to or between printed circuits H05K1/11, H01R12/00
• CPC Class Codes: H05K 2201/09954 : More mounting possibilities, e.g. on same place of PCB, or by using different sets of edge pads
• CPC Class Codes: H05K 2201/10189 : Non-printed connector
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.

Claims

1. An integrated-circuit memory device comprising:

an input to receive memory-width configuration value;

data terminals to exchange data with another device;

a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; and

a data control circuit coupling the physical banks with the data terminals, the data control circuit supporting first and second width configurations responsive to the configuration value;

wherein;

in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data terminals, and the plurality of physical banks collectively provide a first memory depth, and

in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks per read operation and the data terminals, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and

wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operation in the first width configuration and loads a second page of sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page.

2. The memory device of claim 1, further comprising a wire-bonding option to receive the memory-width configuration value.

3. The memory device of claim 1, further comprising a metal layer connection to receive the memory-width configuration value.

4. The memory device of claim 1, wherein the physical banks further comprise a row decoder, and wherein the data control circuit minimizes row-access power in the first width configuration by limiting row accesses to the first integer number of the physical banks.

5. The memory device of claim 1, wherein the second integer is at least two, each physical bank is of a physical-bank width, and wherein the data control circuit combines the second integer number of physical banks into a logical bank of the second data width.

6. The memory device of claim 5, wherein the logical bank consists of four of the physical banks.

7. The memory device of claim 1, wherein the data control circuit supports exactly three width configurations, including the first and second width configurations and a third width configuration, wherein in the third width configuration, the data control circuit conveys data of a third data width, wider than the second data width, between a third integer number of the physical banks and the data terminals.

8. The memory device of claim 7, wherein the second data width is twice the first data width, and the third data width is twice the second data width.

9. The memory device of claim 1, further comprising latches disposed between the data control circuit and the data terminals.

10. The memory device of claim 1, further comprising data buffers disposed between the data control circuit and the data terminals.

11. The memory device of claim 1, wherein the data control circuit comprises a crossbar switch.

12. The memory device of claim 1, further comprising an address buffer, to store memory addresses, connected to the data control circuit.

13. The memory device of claim 12, wherein the data control circuit selects between groups of the physical banks responsive to a bit of the memory addresses.

14. The memory device of claim 13, wherein the groups are of the first integer number in the first width configuration and are of the second integer number in the second width configuration.

15. The memory device of claim 1, embodied as a dynamic random access memory device.

16. A memory module comprising:

a printed-circuit board supporting conductive traces and including module pins; and

memory devices disposed on the printed-circuit board and having data pins connected to the module pins via the conductive traces, each memory device including;

an input to receive memory-width configuration value;

a plurality of physical banks, each physical bank including columns of memory cells coupled to corresponding sense amplifiers; and

a data control circuit coupling the physical banks with the data pins, the data control circuit supporting first and second width configurations responsive to the configuration value;

wherein, for each memory device;

in the first width configuration, the data control circuit conveys data of a first data width between a first integer number of the physical banks per read operation and the data pins, and the plurality of physical banks collectively provide a first memory depth, and

in the second width configuration, the data control circuit conveys data of a second data width between a second integer number of the physical banks and the data pins, the second data width wider than the first data width, the second integer number larger than the first integer number, and the plurality of physical banks collectively provide a second memory depth; and

wherein the memory device loads a first page of sense amplifiers in the first number of the physical banks for activate operations in the first width configuration and loads a second page of the sense amplifiers in the second number of physical banks for activate operations in the second width configuration, the first page smaller than the second page.

17. The memory module of claim 16, further comprising a wire-bonding option to receive the memory-width configuration value.

18. The memory module of claim 16, wherein the physical banks further comprise a row decoder, and wherein the data control circuit minimizes row-access power in the first width configuration by limiting row accesses to the first integer number of the physical banks.

19. The memory module of claim 16, wherein the second integer is at least two, each physical bank is of a physical-bank width, and wherein the data control circuit combines the second integer number of physical banks into a logical bank of the second data width.

20. The memory module of claim 19, wherein the logical bank consists of four of the physical banks.