Very long instruction word (VLIW) processor with power management, and apparatus and method of power management therefor
First Claim
1. A power management apparatus, for use in a very long instruction word (VLIW) processor, wherein the power management apparatus comprises:
- an instruction transcoder for rearranging valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor; and
a power reduction controller for selectively performing power reduction control on the at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package, according to the transcoded instruction package.
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Abstract
A very long instruction word (VLIW) processor and an apparatus with power management and a method of power management therefor are provided in consistent with the exemplary embodiments of the disclosure. The power management method includes the following steps. Valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package are rearranged to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor. Power reduction control is selectively performed on at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package.
28 Citations
34 Claims
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1. A power management apparatus, for use in a very long instruction word (VLIW) processor, wherein the power management apparatus comprises:
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an instruction transcoder for rearranging valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor; and a power reduction controller for selectively performing power reduction control on the at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package, according to the transcoded instruction package. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A power management method, for use in a VLIW processor, wherein the power management method comprises:
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rearranging valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package to output a transcoded instruction package, wherein the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponds to at least one execution unit, which is to be placed in power reduction state, of a VLIW processor; and selectively performing power reduction control on the at least one execution unit corresponding to the at least one NOP instruction of the transcoded instruction package, according to the transcoded instruction package. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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22. A very long instruction word (VLIW) processor, comprising:
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a read operand stage; a plurality of execution units coupled to the read operand stage; an instruction transcoder, wherein the read operand stage is coupled between the instruction transcoder and the execution units, the instruction transcoder rearranges valid instruction(s) and no operation (NOP) instruction(s) of an input instruction package to output a transcoded instruction package, which is executed by the execution units, and the transcoded instruction package by the rearrangement has its NOP instruction(s) corresponding to at least one of the execution units, which is to be placed in power reduction state; and a power reduction controller for selectively performing power reduction control on the at least one execution unit corresponding to at least one NOP instruction of the transcoded instruction package according to the transcoded instruction package. - View Dependent Claims (23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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Specification