Bad page management in memory device or system
First Claim
Patent Images
1. A memory device, comprising:
- a memory cell array comprising a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells;
a bad page map that stores bad page location information indicating whether each of the pages of the first memory block is good or bad;
a first page control unit that generates a first access page address to block access to a fail page address of the first memory block; and
a second page control unit that generates a second access page address to allow access to a pass page address of the second memory block,wherein the fail page address of the first memory block is replaced by the pass page address of the second memory block according to the bad page location information, andwherein the second page control unit comprises;
a first storage unit that stores a memory access page address received from an external source;
a second storage unit that stores the pass page address of the second memory block that replaces the fail page address of the first memory block;
a selection control unit that stores a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block; and
a selection unit that selects the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputs a result of the selection as the second access page address.
1 Assignment
0 Petitions
Accused Products
Abstract
A memory device comprises a memory cell array and a bad page map. The memory cell array comprises a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells. The bad page map stores bad page location information indicating whether each of the pages of the first memory block is good or bad. A fail page address of the first memory block is replaced by a pass page address of the second memory block according to the bad page location information.
-
Citations
18 Claims
-
1. A memory device, comprising:
-
a memory cell array comprising a plurality of memory cells arranged in pages and columns, wherein the memory cell array is divided into a first memory block and a second memory block each corresponding to an array of the memory cells; a bad page map that stores bad page location information indicating whether each of the pages of the first memory block is good or bad; a first page control unit that generates a first access page address to block access to a fail page address of the first memory block; and a second page control unit that generates a second access page address to allow access to a pass page address of the second memory block, wherein the fail page address of the first memory block is replaced by the pass page address of the second memory block according to the bad page location information, and wherein the second page control unit comprises; a first storage unit that stores a memory access page address received from an external source; a second storage unit that stores the pass page address of the second memory block that replaces the fail page address of the first memory block; a selection control unit that stores a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block; and a selection unit that selects the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputs a result of the selection as the second access page address. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A memory system, comprising:
-
a memory device comprising a first memory block, a second memory block, and a bad page map that stores bad page location information of the first memory block; a memory controller that stores fail page addresses of the first memory block and pass page addresses of the second memory block that respectively replace the fail page addresses, according to bit information transmitted by the bad page map; a first page control unit that generates a first access page address to block an address to a fail page address of the first memory block; and a second page control unit that generates a second access page address to allow access to a pass page address of the second memory block, wherein the second page control unit comprises; a first storage unit that stores a memory access page address received from an external source; a second storage unit that stores the pass page address of the second memory block that replaces the fail page address of the first memory block; a selection control unit that stores a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block; and a selection unit that selects the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputs a result of the selection as the second access page address. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A method of operating a memory device comprising a memory cell array and a bad page map, comprising:
-
storing, in the bad page map, bad page location information indicating whether each page in a first memory block of the memory cell array is good or bad; and replacing a fail page address of the first memory block with a pass page address in a second memory block of the memory cell array according to the bad page location information; wherein replacing the fail page address comprises generating a first access page address to block an address to the fail page address of the first memory block, and generating a second access page address to allow access to the pass page address of the second memory block, and wherein generating the second access page address comprises storing a memory access page address received from an external source, storing the pass page address of the second memory block that replaces the fail page address of the first memory block, storing a control signal for instructing the fail page address of the first memory block to be replaced by the pass page address of the second memory block, selecting the memory access page address stored in the first storage unit or the pass page address of the second memory block stored in the second storage unit and outputting a result of the selection as the second access page address. - View Dependent Claims (16, 17, 18)
-
Specification