Method of identifying and protecting the integrity of a set of source data

• US 8,769,373 B2
• Filed: 10/05/2010
• Issued: 07/01/2014
• Est. Priority Date: 03/22/2010
• Status: Active Grant

• Current Assignee: LRDC Systems LLC
• Original Assignee: Cleon L. Rogers Jr
• Inventors: Rogers, Cleon L. Jr., Logan, Glen T.
• Primary Examiner(s): Alphonse, Fritz
• Application Number:
  US13/514,178
• Publication Number:
  US 20130019140A1
• Time in Patent Office: 1,365 Days
• Field of Search: 714/758, 714/721, 714/766, 714/800, 714/752, 714/776, 714/781, 714/761, 714/774
• US Class Current: 714/758
• CPC Class Codes: G06F 21/00 Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
• CPC Class Codes: G06F 21/572 Secure firmware programming, e.g. of basic input output system [BIOS]
• CPC Class Codes: G06F 21/64 Protecting data integrity, e.g. using checksums, certificates or signatures
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/63 Joint error correction and other techniques H03M13/31 and H03M13/33 take precedence

Abstract

A method of identifying and protecting the integrity of a set of source data which produces and combines an identification signature with a detection and correction remainder and extends the existing capability of some information assurance methods.

Claims

1. A method of identifying and protecting the integrity of a set of source data, comprising the steps of:

(a) passing the source data through a transformation utilizing at least one of an interleaver comprising a Forney interleaver, a 2-bit rotation, a criss-cross wiring matrix, a serial-to-parallel data converter whose output is interleaved by a criss-cross wiring matrix, a serial-to-parallel data converter whose output is interleaved by an M-by-N FLASH memory, parallel data lines input to an M-by-N FLASH whose output is interleaved by an M-by-N FLASH memory, an interleaver comprising a serial-to-parallel data converter whose output is interleaved by an M-by-N RAM memory, or parallel data lines input to an M-by-N RAM memory whose output is interleaved by an M-by-N RAM memory to produce a transformed set of source data, where m<

n, m>

n, or m=n;

(b) distorting said transformed set of source data with a distortion function to produce an intermediate set of source data; and

(c) passing the intermediate set of source data through an error detection and correction (EDAC) algorithm to produce a remainder and attaching said remainder to the set of source data to produce an encoded set of source data.

2. The method of claim 1, further comprising the step of passing the encoded set of source data through a second EDAC algorithm to produce a second remainder and attaching said second remainder to the encoded set of source data.

3. The method of claim 1 wherein said transformation comprises an interleaver comprising a 2-bit rotation.

4. The method of claim 1 wherein the distortion function of step (b) comprises an exclusive OR operation between said transformed set of source data and a binary pattern.

5. The method of claim 1 wherein said set of source data is an embedded set of source data.

6. The method of claim 5 wherein said remainder is calculated prior to embedding said set of source data.

7. The method of claim 1 wherein said transformation comprises an interleaver comprising a Forney interleaver.

8. The method of claim 1, wherein said transformation comprises an interleaver comprising a serial-to-parallel data converter whose output is interleaved by a criss-cross wiring matrix.

9. The method of claim 1, wherein said transformation comprises an interleaver comprising a serial-to-parallel data converter whose output is interleaved by an N-by-N FLASH memory.

10. The method of claim 1, wherein said transformation comprises an interleaver comprising a serial-to-parallel data converter whose output is interleaved by an N-by-N RAM memory.

11. The method of claim 4, wherein said binary pattern is extracted from an N-by-N RAM memory.

12. The method of claim 1, wherein said transformation comprises an affine transformation.

13. The method of claim 1, wherein said transformation comprises a non-axiomatic transformation.

14. The method of claim 1, wherein said transformation is selected from the group consisting of transforms without an inverse function, without preserving rigid motion, and a LangGanong Transform matrix.

15. The method of claim 2, wherein said EDAC algorithm and said second EDAC algorithm are the same.

16. The method of claim 2, wherein said EDAC algorithm and said second EDAC algorithm are different.

17. The method of claim 16, wherein said first EDAC algorithm comprises a first polynomial and said second EDAC algorithm comprises a second polynomial that is different from said first polynomial.

18. The method of claim 1 wherein said EDAC algorithm is selected from the group comprising a CRC algorithm, Reed-Solomon encoding, Viterbi algorithms, Turbo encoding, MD5 algorithms and SHA-1 hash algorithms.

19. The method of claim 5 wherein steps (a) and (b) are programmable.

20. The method of claim 17 wherein said remainders are verified periodically.

21. The method of claim 17 wherein said remainders are verified aperiodically.

22. The method of claim 1, further comprising the step of verifying the integrity of said source data comprising the steps of recalculating said remainder, comparing the recalculated value of said remainder with the value of said remainder calculated in step (c) and providing an indicator that the comparison shows that said remainder and said recalculated value of said remainder are not the same.

23. The method of claim 22, further comprising the step of providing said remainder to a sink.

24. The method of claim 23, wherein said sink is selected from the group consisting of a display means, placement on a serial bus, placement on a parallel bus, and control logic.

25. The method of claim 22, further comprising the step of providing said remainder in response to a request.

26. A computerized method of identifying and protecting the integrity of a set of source data utilizing a computer processor and a memory, comprising the steps of:

(a) passing the source data through a transformation at the processor to produce a transformed set of source data stored at the memory;

(b) distorting said transformed set of source data with a distortion function at the processor to produce an intermediate set of source data stored at the memory; and

(c) passing the intermediate set of source data through an error detection and correction (EDAC) algorithm at the processor to produce a remainder and attaching said remainder to the set of source data stored at the memory to produce an encoded set of source data stored at the memory.

27. The method of claim 26, further comprising the step of passing the encoded set of source data through a second EDAC algorithm at the processor to produce a second remainder and attaching said second remainder to the encoded set of source data stored at the memory.

28. The method of claim 26, further comprising the step of verifying the integrity of said source data comprising the steps of recalculating said remainder at the processor, comparing the recalculated value of said remainder with the value of said remainder calculated in step (c) at the processor, and providing at an output device an indicator that the comparison shows that said remainder and said recalculated value of said remainder are not the same.