Multi-write endurance and error control coding of non-volatile memories

• US 8,769,374 B2
• Filed: 10/13/2010
• Issued: 07/01/2014
• Est. Priority Date: 10/13/2010
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Franceschini, Michele M., Jagmohan, Ashish
• Primary Examiner(s): GUYTON, PHILIP A
• Application Number:
  US12/903,695
• Publication Number:
  US 20120096328A1
• Time in Patent Office: 1,357 Days
• Field of Search: 714/763, 714/773
• US Class Current: 714/763
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 2029/0411 Online error correction

Abstract

Multi-write endurance and error control coding of non-volatile memories including a method for receiving write data and a write address of a memory page in a memory. The write data is partitioned into a plurality of sub-blocks, each sub-block including q bits of the write data. Error correction bits are generated at the computer in response to the sub-blocks and to an error correction code (ECC). At least one additional sub-block containing the error correction bits are appended to the partitioned write data and a write word is generated. The write word is generated by performing for each of the sub-blocks: selecting a codeword such that the codeword encodes the sub-block and is consistent with current electrical charge levels of the plurality of memory cells associated with the memory page; concatenating the selected codewords to form the write word; and writing the write word to the memory page.

Claims

1. A computer implemented method for storing data, the method comprising:

receiving write data comprising a plurality of bits;

receiving a write address of a memory page in a memory, the memory page associated with a plurality of memory cells having current electrical charge levels;

partitioning, at a computer, the write data into a plurality of q-bit sub-blocks, each q-bit sub-block comprising q bits of the write data;

generating, at the computer, error correction bits in response to the q-bit sub-blocks and to an error correction code (ECC);

appending at least one additional q-bit sub-block containing the error correction bits to the partitioned write data;

generating a write word, the generating a write word comprising;

performing for each of the q-bit sub-blocks including the at least one additional q-bit sub-block containing the error correction bits;

selecting a codeword such that the codeword encodes the q-bit sub-block and is consistent with the current electrical charge levels of the plurality of memory cells associated with the memory page; and

concatenating the selected codewords to form the write word; and

writing the write word to the memory page.

2. The method of claim 1, wherein at least one of the q-bit sub-blocks comprising q bits of the write data is modified or replaced by the generated error correction bits.

3. The method of claim 1, wherein the memory page is in an erased state prior to the writing.

4. The method of claim 1, wherein the memory page is in a previously written state prior to the writing.

5. The method of claim 1, wherein the write data is compressed prior to the partitioning.

6. The method of claim 1, wherein the memory is implemented by a flash memory device.

7. The method of claim 1, wherein the memory is implemented by a single level cell not-and (NAND) flash memory device.

8. The method of claim 1, wherein the memory is implemented by a multi-level cell NAND flash memory device.

9. A system comprising:

a receiver for receiving write data and a write address of a memory page in a memory, the memory page associated with a plurality of memory cells having current electrical charge levels;

an encoder communicatively coupled to the memory, the encoder for performing a method comprising;

partitioning the write data into a plurality of q-bit sub-blocks, each q-bit sub-block comprising q bits of the write data;

generating error correction bits in response to the q-bit sub-blocks and to an error correction code (ECC);

appending at least one additional q-bit sub-block containing the error correction bits to the partitioned write data;

generating a write word, the generating a write word comprising;

performing for each of the q-bit sub-blocks including the at least one additional q-bit sub-block containing the error correction bits;

selecting a codeword such that the codeword encodes the q-bit sub-block and is consistent with the current electrical charge levels of the plurality of memory cells associated with the memory page; and

concatenating the selected codewords to form the write word; and

writing the write word to the memory page.

10. The system of claim 9, wherein at least one of the q-bit sub-blocks comprising q bits of the write data is modified or replaced by the generated error correction bits.

11. The system of claim 9, wherein the memory page is in an erased state prior to the writing.

12. The system of claim 9, wherein the memory page is in a previously written state prior to the writing.

13. The system of claim 9, wherein the write data is compressed prior to the partitioning.

14. The system of claim 9, wherein the memory is a single level cell not-and (NAND) flash memory device.

15. The system of claim 9, wherein the memory is a multi-level cell NAND flash memory device.

16. A computer implemented method for retrieving data from memory, the method comprising:

receiving a read address of a memory page in a memory;

retrieving a read word from the memory page, the read word comprising a plurality of multi-write endurance (MWE) codewords including at least one MWE codeword that corresponds to error correction bits;

determining, at a computer, that each of the MWE codewords is in a set of MWE codewords used to generate the read word;

generating read data, at the computer, the generating read data comprising;

performing for each of the MWE codewords;

selecting a sub-block comprising data that corresponds to the MWE codeword;

concatenating the sub-blocks to generate the ECC codeword;

performing error correction code (ECC) processing on the ECC codeword; and

removing the error correction bits from the ECC codeword resulting in the read data; and

outputting the read data.

17. The method of claim 16, further comprising:

determining that a MWE codeword is not in the set of MWE codewords used to encode the read data; and

marking the MWE codeword that is not in the set of MWE codewords used to encode the read data as an error, wherein an erased sub-block is substituted for the marked MWE codeword and the ECC processing is further responsive to the erased sub-block.

18. The method of claim 16, wherein the ECC processing corrects at least one error in the read data in response to determining that the read data contains at least one error.

19. The method of claim 16, wherein the memory is a single level cell not-and (NAND) flash memory device.

20. The system of claim 16, wherein the memory is a multi-level cell NAND flash memory device.

21. A system for retrieving data comprising:

a receiver for receiving a read address of a memory page in a memory;

a decoder communicatively coupled to the memory, the decoder for performing a method comprising;

retrieving a read word from the memory page, the read word comprising a plurality of multi-write endurance (MWE) codewords including at least one MWE codeword that corresponds to error correction bits;

determining, at a computer, that each of the MWE codewords is in a set of MWE codewords used to generate the read word;

generating read data, at the computer, the generating read data comprising;

performing for each of the MWE codewords;

selecting a sub-block comprising data that corresponds to the MWE codeword;

concatenating the sub-blocks;

performing error correction code (ECC) processing on the read data in response to the error correction bits and to the sub-blocks; and

removing the error correction bits from the read data; and

outputting the read data.

22. The system of claim 21, wherein the method further comprises:

determining that a MWE codeword is not in the set of MWE codewords used to encode the read data; and

marking the MWE codeword that is not in the set of MWE codewords used to encode the read data as an error, wherein an erased sub-block is substituted for the marked MWE codeword and the ECC processing is further responsive to the erased sub-block.

23. The system of claim 21, wherein the ECC processing corrects at least one error in the read data in response to determining that the read data contains at least one error.

24. The method of claim 21, wherein the memory is a single level cell not-and (NAND) flash memory device.

25. The system of claim 21, wherein the memory is a multi-level cell NAND flash memory device.