×

Multi-write endurance and error control coding of non-volatile memories

  • US 8,769,374 B2
  • Filed: 10/13/2010
  • Issued: 07/01/2014
  • Est. Priority Date: 10/13/2010
  • Status: Active Grant
First Claim
Patent Images

1. A computer implemented method for storing data, the method comprising:

  • receiving write data comprising a plurality of bits;

    receiving a write address of a memory page in a memory, the memory page associated with a plurality of memory cells having current electrical charge levels;

    partitioning, at a computer, the write data into a plurality of q-bit sub-blocks, each q-bit sub-block comprising q bits of the write data;

    generating, at the computer, error correction bits in response to the q-bit sub-blocks and to an error correction code (ECC);

    appending at least one additional q-bit sub-block containing the error correction bits to the partitioned write data;

    generating a write word, the generating a write word comprising;

    performing for each of the q-bit sub-blocks including the at least one additional q-bit sub-block containing the error correction bits;

    selecting a codeword such that the codeword encodes the q-bit sub-block and is consistent with the current electrical charge levels of the plurality of memory cells associated with the memory page; and

    concatenating the selected codewords to form the write word; and

    writing the write word to the memory page.

View all claims
  • 7 Assignments
Timeline View
Assignment View
    ×
    ×