Method, system, and computer program product for preparing multiple layers of semiconductor substrates for electronic designs

• US 8,769,453 B2
• Filed: 10/29/2010
• Issued: 07/01/2014
• Est. Priority Date: 12/29/2006
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Scheffer, Louis K., White, David
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US12/916,469
• Publication Number:
  US 20110046767A1
• Time in Patent Office: 1,341 Days
• Field of Search: 716/51, 716/52, 716/106, 716/111, 716/124, 716/132, 716/136
• US Class Current: 716/106
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Disclosed is an improved method, system, and computer program product for preparing multiple levels of semiconductor substrates for three-dimensional IC integration. Some embodiments utilize the process and design models to check and fabricate the insulating dielectric layer (IDL) separating the first and the second film stacks on separate substrates and then prepare the surface of the IDL to receive an additional layer of semiconductor substrate for further fabrication of the chips. Yet some other embodiments further employ the design and process models to ensure the IDL and the semiconductor substrate are sufficiently flat, or are otherwise satisfactory, so the three-dimensional integrated circuits meet the reliability, manufacturability, yield, or performance requirements. Yet some other embodiments further employ design and process models to place the vias connecting the multiple film stacks.

Claims

1. A machine implemented method for integrating three-dimensional integrated circuits, comprising:

using at least one processor that is configured or programmed for performing a process comprising;

identifying or generating one or more models to identify a first process for manufacturing a first level of an electronic circuit, in which the first level of the electronic circuit is created on top of a first semiconductor substrate;

identifying or generating one or more models to identify a second process for manufacturing a second level of the electronic circuit;

generating electronic design data for an insulating dielectric layer (IDL) atop the first level of the electronic circuit;

generating the electronic design data for creating a second semiconductor substrate between the insulating dielectric layer (IDL) and the second level that is created atop the second semiconductor substrate; and

generating the electronic design data for manufacturing a via or an interconnection which electrically connects the first level and the second level of the electronic circuit.

2. The method of claim 1, the process further comprising:

generating the electronic design data for preparing the insulating dielectric layer (IDL) to enable the insulating dielectric layer to receive the second semiconductor substrate based upon the first level of the electronic design or the first semiconductor substrate.

3. The method of claim 1, the process further comprising:

generating the electronic design data for creating a buffer layer atop the second semiconductor substrate to enable reception of the second level of the electronic circuit.

4. The method of claim 1, in which the process for generating the electronic design data for creating the second semiconductor substrate is based at least in part upon the first level of the electronic circuit or the first semiconductor substrate.

5. The machine implemented method of claim 1, the process further comprising:

identifying or generating one or more models for determining a process or technique for preparing the second semiconductor substrate layer by analyzing the second semiconductor substrate layer with an additional concurrent model for the process or technique.

6. The machine implemented method of claim 1, in which the process further comprises determining whether the second semiconductor substrate layer meets a criterion that further includes:

identifying or generating one or more models for determining a buffer layer process which causes a buffer layer to be created atop the second semiconductor substrate layer based upon a concurrent model for the buffer layer process, in which

the buffer layer comprises a germanium layer, a silicon-germanium layer, or an inter- layer dielectric (ILD) layer.

7. The machine implemented method of claim 6, the process further comprising:

identifying or generating one or more models for determining whether the buffer layer meets a second criterion to receive the second level of the electronic circuit, in which

the second criterion comprises a performance, manufacturability, or reliability requirement for the second level of the electronic design or for the electronic design.

8. An apparatus for integrating three-dimensional integrated circuits, comprising:

at least one processor that is at least to;

identify or generate one or more models to identify a first process for manufacturing a first level of an electronic circuit, in which the first level of the electronic circuit is created on top of a first semiconductor substrate;

identify or generate the one or more models to identify a second process for manufacturing a second level of the electronic circuit;

generate electronic design data for an insulating dielectric layer (IDL) atop the first level of the electronic circuit;

generate the electronic design data for a second semiconductor substrate between the insulating dielectric layer and the second level that is created atop the second semiconductor substrate; and

generate the electronic design data for manufacturing a via or an interconnection which electrically connects the first level and the second level of the electronic circuit.

9. The apparatus of claim 8, wherein the at least one processor is further to:

identify or generate the one or more models to prepare the insulating dielectric layer (IDL) to enable the insulating dielectric layer (IDL) to receive the second semiconductor substrate based upon the first level of the electronic design or the first semiconductor substrate.

10. The apparatus of claim 8, wherein the at least one processor is further to:

generate the electronic design data for creating a buffer layer atop the second semiconductor substrate to enable reception of the second level of the electronic circuit.

11. The apparatus of claim 8, in which the at least one processor that is to generate the electronic design data for creating the second semiconductor substrate is to base at least in part upon the first level of the electronic circuit or the first semiconductor substrate.

12. The apparatus of claim 8, wherein the at least one processor is further to:

identify or generate one or more models for determining a process or technique for preparing the second semiconductor substrate layer by analyzing the second semiconductor substrate layer in conjunction with an additional concurrent model for the process or technique.

13. The apparatus of claim 8, wherein the at least one processor is further to:

identify or generate one or more models for determining a buffer layer process which causes a buffer layer to be created atop the second semiconductor substrate layer based upon a concurrent model for the buffer layer process, in which the buffer layer comprises a germanium layer, a silicon-germanium layer, or an inter-layer dielectric (ILD) layer.

14. The apparatus of claim 13, the at least one processor that is further to determine whether the second semiconductor substrate layer meets a criterion is further to:

identify or generate one or more models for determining whether the buffer layer meets a second criterion to receive the second level of the electronic circuit, in which

the second criterion comprises a performance, manufacturability, or reliability requirement for the second level of the electronic design or for the electronic design.

15. A computer program product comprising a non-transitory computer readable storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the at least one processor to perform a process for integrating three-dimensional integrated circuits, the process comprising:

identifying or generating one or more models to identify a first process for manufacturing a first level of an electronic circuit, in which the first level of the electronic circuit is created on top of a first semiconductor substrate;

identifying or generating one or more models to identify a second process for manufacturing a second level of the electronic circuit;

generating electronic design data for an insulating dielectric layer (IDL) atop the first level of the electronic circuit;

generating the electronic design data for creating a second semiconductor substrate between the insulating dielectric layer (IDL) and the second level that is created atop the second semiconductor substrate; and

generating the electronic design data for manufacturing a via or an interconnection which electrically connects the first level and the second level of the electronic circuit.

16. The computer program product of claim 15, the process further comprising:

generating the electronic design data for preparing the insulating dielectric layer (IDL) to enable the insulating dielectric layer (IDL) to receive the second semiconductor substrate based upon the first level of the electronic design or the first semiconductor substrate.

17. The computer program product of claim 15, the process further comprising:

generating the electronic design data for creating a buffer layer atop the second semiconductor substrate to enable reception of the second level of the electronic circuit.

18. The computer program product of claim 15, in which the process for generating the electronic design data for creating a second semiconductor substrate is based at least in part upon the first level of the electronic circuit or the first semiconductor substrate.

19. The computer program product of claim 15, the process further comprising:

identifying or generating one or more models for determining a process or technique for preparing the second semiconductor substrate layer by analyzing the second semiconductor substrate layer in conjunction with an additional concurrent model for the process or technique.

20. The computer program product of claim 19, in which the process further comprises determining whether the second semiconductor substrate layer meets a criterion that further includes:

identifying or generating one or more models for determining a buffer layer process which causes a buffer layer to be created atop the second semiconductor substrate layer based upon a concurrent model for the buffer layer process, in which

the buffer layer comprises a germanium layer, a silicon-germanium layer, or an inter-layer dielectric (ILD) layer.