Apparatus and method for forming semiconductor contacts

• US 8,772,109 B2
• Filed: 10/24/2012
• Issued: 07/08/2014
• Est. Priority Date: 10/24/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Colinge, Jean-Pierre
• Primary Examiner(s): KUSUMAKAR, KAREN M
• Application Number:
  US13/659,836
• Publication Number:
  US 20140110755A1
• Time in Patent Office: 622 Days
• Field of Search: 438/196, 438/212, 438/268, 438/269, 257/192, 257/263
• US Class Current: 438/269
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/02667 Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
• CPC Class Codes: H01L 21/30625 With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method for forming semiconductor contacts comprises forming a germanium fin structure over a silicon substrate, depositing a doped amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure and performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.

Claims

1. A method comprising:

forming a germanium fin structure over a silicon substrate, wherein the germanium fin structure comprises;

a channel connected between a first drain/source region and a second drain/source region;

depositing an N+ amorphous silicon layer over the first drain/source region and the second drain/source region at a first temperature, wherein the first temperature is lower than a melting point of the germanium fin structure; and

performing a solid phase epitaxial regrowth process on the amorphous silicon layer at a second temperature, wherein the second temperature is lower than the melting point of the germanium fin structure.

2. The method of claim 1, wherein:

the first temperature is in a range from about 550 degrees to about 600 degrees.

3. The method of claim 1, wherein:

the second temperature is in a range from about 620 degrees to about 650 degrees.

4. The method of claim 1, further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the germanium fin structure is embedded in the ILD layer;

forming a first opening over the first drain/source region in the ILD layer;

forming a second opening over the second drain/source region in the ILD layer;

filling the first opening and the second opening with N+ amorphous silicon;

performing a solid phase epitaxial regrowth process on N+ amorphous silicon to form a N+ silicon region; and

performing a CMP process on the ILD layer until the N+ silicon region is exposed.

5. The method of claim 4, wherein:

the N+ silicon region wraps the first drain/source region around three sides.

6. The method of claim 4, wherein:

the N+ silicon region is formed over the first drain/source region.

7. A method comprising:

forming a germanium fin over a silicon substrate, wherein the germanium fin comprises;

a first drain/source region;

a second drain/source region; and

a channel coupled between the first drain/source region and the second drain/source region;

forming a gate structure over the channel, wherein the gate structure comprises;

a gate dielectric layer; and

a gate electrode layer formed over the gate dielectric layer;

depositing a first amorphous silicon layer over the first drain/source region at a first temperature;

depositing a second amorphous silicon layer over the second drain/source region at a second temperature; and

performing a solid phase epitaxial regrowth process on the first amorphous silicon layer and the second amorphous silicon layer at a third temperature.

8. The method of claim 7, wherein:

the first temperature is in a range from about 550 degrees to about 600 degrees;

the second temperature is in a range from about 550 degrees to about 600 degrees; and

the third temperature is in a range from about 620 degrees to about 650 degrees.

9. The method of claim 7, further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the first drain/source region and the second drain/source region are embedded in the ILD layer;

forming a first opening over the first drain/source region, wherein the first opening is of a dimension approximately equal to a dimension of the first drain/source region;

forming a second opening over the second drain/source region, wherein the second opening is of a dimension approximately equal to a dimension of the second drain/source region;

depositing amorphous silicon in the first opening and the second opening; and

performing a solid phase epitaxial regrowth process on the amorphous silicon.

10. The method of claim 7, further comprising:

depositing an inter-layer dielectric (ILD) layer over the substrate, wherein the first drain/source region and the second drain/source region are embedded in the ILD layer;

forming a first opening over the first drain/source region, wherein the first opening is of a dimension greater than a dimension of the first drain/source region;

forming a second opening over the second drain/source region, wherein the second opening is of a dimension greater than a dimension of the second drain/source region;

depositing amorphous silicon in the first opening and the second opening; and

performing a solid phase epitaxial regrowth process on the amorphous silicon.

11. The method of claim 10, further comprising:

after the step of performing a solid phase epitaxial regrowth process on the amorphous silicon, applying a CMP process to the ILD layer; and

forming a first N+ silicon structure over the first drain/source region, wherein the first N+ silicon structure wraps the first drain/source region around three sides; and

forming a second N+ silicon structure over the second drain/source region, wherein the second N+ silicon structure wraps the second drain/source region around three sides.

12. The method of claim 11, further comprising:

forming a first metal contact over the first N+ silicon structure; and

forming a second metal contact over the second N+ silicon structure.