Metal gate semiconductor device and method of fabricating thereof
First Claim
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1. A method, comprising:
- forming a first work function metal layer on a first region of the substrate, wherein the first region is defined to include devices of one of a p-type and an n-type;
forming a metal layer on the first work function metal layer in the first region and on a second region of the substrate, wherein the second region is defined to include devices of the other of a p-type and an n-type;
forming a dummy layer on the metal layer in the first region and the second region;
patterning the dummy layer, first work function metal layer, and the metal layer to form a first gate structure in the first region and a second gate structure in the second region of the substrate, wherein the first gate structure includes the dummy layer, the first work function metal layer and the metal layer and the second gate structure includes the dummy layer and the metal layer;
after forming the first gate structure and the second gate structure, removing the dummy layer to expose the metal layer; and
treating the metal layer in the first region and the second region.
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Abstract
A method of semiconductor fabrication including forming a first work function metal layer on a first region of the substrate and forming a metal layer on the first work function metal layer and on a second region of the substrate. A dummy layer is formed on the metal layer. The layers are then patterned to form a first gate structure in the first region and a second gate structure in the second region of the substrate. The dummy layer is then removed to expose the metal layer, which is treated. The treatment may be an oxygen treatment that allows the metal layer to function as a second work function layer.
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Citations
20 Claims
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1. A method, comprising:
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forming a first work function metal layer on a first region of the substrate, wherein the first region is defined to include devices of one of a p-type and an n-type; forming a metal layer on the first work function metal layer in the first region and on a second region of the substrate, wherein the second region is defined to include devices of the other of a p-type and an n-type; forming a dummy layer on the metal layer in the first region and the second region; patterning the dummy layer, first work function metal layer, and the metal layer to form a first gate structure in the first region and a second gate structure in the second region of the substrate, wherein the first gate structure includes the dummy layer, the first work function metal layer and the metal layer and the second gate structure includes the dummy layer and the metal layer; after forming the first gate structure and the second gate structure, removing the dummy layer to expose the metal layer; and treating the metal layer in the first region and the second region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method, comprising:
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forming a portion of a first gate structure associated with a NMOS transistor, wherein the portion of the first gate structure includes a gate dielectric, a capping layer, a first metal layer on the capping layer, and a second metal layer overlying the first metal layer, wherein the first metal layer is an n-type metal; forming a portion of a second gate structure associated with a PMOS transistor, wherein the portion of the second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric, and wherein the second gate structure does not include the first metal layer; forming a dummy layer on the portion of the first gate structure and on the portion of the second gate structure overlying the second metal layer; removing the dummy layer simultaneously in both the first gate structure and the second gate structure to form trenches; and filling the trenches with a fill metal. - View Dependent Claims (10, 11, 12, 13, 14)
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15. A method, comprising:
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forming a portion of a first gate structure associated with a first type of transistor, wherein the portion of the first gate structure includes a capping layer, a first metal layer having a first type of work function on the capping layer, and a second metal layer overlying the first metal layer; forming a portion of a second gate structure associated with a second type of transistor, wherein the portion of the second gate structure includes the gate dielectric and the second metal layer formed on the gate dielectric; treating the second metal layer of the first gate structure and the second gate structure; and forming a fill layer on the treated second metal layer of the first gate structure and the second gate structure. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification