Semiconductor device and method for manufacturing the same
First Claim
1. A method for manufacturing a semiconductor device, comprising:
- providing a silicon substrate having {100} crystal indices with a gate stack structure formed thereon;
forming a second isolation region within the silicon substrate wherein the second isolation region comprises a second dielectric layer;
forming an interlayer dielectric layer to cover a top surface of the silicon substrate;
forming a first trench in the interlayer dielectric layer and/or in the gate stack structure above the second isolation region, and the second dielectric layer is exposed at a bottom of the first trench, wherein the first trench has an extension direction being along <
110>
crystal direction and perpendicular to that of the gate stack structure; and
filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile-stressed dielectric layer.
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Abstract
The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device comprises: providing a silicon substrate having a gate stack structure formed thereon and having {100} crystal indices; forming an interlayer dielectric layer coving a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure, the first trench having an extension direction being along <110> crystal direction and perpendicular to that of the gate stack structure; and filling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile stress dielectric layer. The present invention introduces a tensile stress in the transverse direction of a channel region by using a simple process, which improves the response speed and performance of semiconductor devices.
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Citations
16 Claims
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1. A method for manufacturing a semiconductor device, comprising:
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providing a silicon substrate having {100} crystal indices with a gate stack structure formed thereon; forming a second isolation region within the silicon substrate wherein the second isolation region comprises a second dielectric layer; forming an interlayer dielectric layer to cover a top surface of the silicon substrate; forming a first trench in the interlayer dielectric layer and/or in the gate stack structure above the second isolation region, and the second dielectric layer is exposed at a bottom of the first trench, wherein the first trench has an extension direction being along <
110>
crystal direction and perpendicular to that of the gate stack structure; andfilling the first trench with a first dielectric layer, wherein the first dielectric layer is a tensile-stressed dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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Specification