Field effect transistor devices with dopant free channels and back gates

• US 8,772,143 B2
• Filed: 11/14/2012
• Issued: 07/08/2014
• Est. Priority Date: 11/14/2012
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Shahidi, Ghavam G.
• Primary Examiner(s): Patel, Reema
• Application Number:
  US13/676,927
• Publication Number:
  US 20140134826A1
• Time in Patent Office: 601 Days
• Field of Search: 438/558, 257/506, 257/510, 257/374
• US Class Current: 438/558
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

A method of forming a back gate transistor device includes forming an open isolation trench in a substrate; forming sidewall spacers in the open isolation trench; and using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants.

Claims

1. A method of forming a back gate transistor device, the method comprising:

forming an open isolation trench in a substrate;

forming sidewall spacers in the open isolation trench; and

using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench that serves as a back gate conductor, wherein the sidewall spacers prevent contamination of a channel region of the back gate transistor device by dopants;

wherein the performing the doping operation further comprises forming a dopant source insulator material within the open isolation trench, performing an annealing operation so as to drive dopants from the dopant source insulator material into the substrate, and performing one of;

recessing a portion of the dopant source insulator material and replacing the same with an undoped insulator material prior to performing the annealing operation;

or

completely removing the dopant source insulator material following the annealing operation.

2. The method of claim 1, wherein the doped well region comprises a p-type region, and the dopant source insulator material comprises boron-doped oxide.

3. The method of claim 1, wherein the doped well region comprises an n-type region, and the dopant source insulator material comprises one or more of arsenic-doped oxide and phosphorous-doped oxide.

4. The method of claim 1, wherein the substrate comprises a semiconductor-on-insulator (SOI) substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer.

5. The method of claim 4, wherein the SOI substrate comprises an extremely thin SOI (ETSOI) substrate, with the active SOI layer having a thickness of about 10 nanometers (nm) or less.

6. The method of claim 4, wherein the open isolation trench is formed completely through the active SOI layer and the BOX layer, and into a portion of the bulk substrate layer such that the sidewall spacers prevent contamination of the active SOI layer and the BOX layer by the dopants.

7. A method of forming a back gate transistor device, the method comprising:

forming a protective pad layer over a semiconductor-on-insulator (SOI) substrate, the SOI substrate having a bulk substrate layer, a buried insulator (BOX) layer formed on the bulk substrate layer, and an active SOI layer formed on the buried insulator layer;

forming an open isolation trench through the protective pad layer, the active SOI layer, the BOX layer, and into a portion of the bulk substrate layer;

forming sidewall spacers in the open isolation trench; and

using the open isolation trench to perform a doping operation so as to define a doped well region below a bottom surface of the isolation trench and the BOX layer, such that the doped well region serves as a back gate conductor, wherein the sidewall spacers prevent contamination of the BOX layer and the active SOI layer device by dopants;

wherein the performing the doping operation further comprises forming a dopant source insulator material within the open isolation trench, performing an annealing operation so as to drive dopants from the dopant source insulator material into the bulk substrate layer, and performing one of;

recessing a portion of the dopant source insulator material and replacing the same with an undoped insulator material prior to performing the annealing operation;

or

completely removing the dopant source insulator material following the annealing operation.

8. The method of claim 7, further comprising refilling the open isolation trench with an undoped insulator material.

9. The method of claim 7, wherein the doped well region comprises a p-type region, and the dopant source insulator material comprises boron-doped oxide.

10. The method of claim 7, wherein the doped well region comprises an n-type region, and the dopant source insulator material comprises one or more of arsenic-doped oxide and phosphorous-doped oxide.

11. The method of claim 7, wherein the SOI substrate comprises an extremely thin SOI (ETSOI) substrate, with the active SOI layer having a thickness of about 10 nanometers (nm) or less.