High performance, high bandgap, lattice-mismatched, GaInP solar cells

• US 8,772,628 B2
• Filed: 01/29/2009
• Issued: 07/08/2014
• Est. Priority Date: 12/30/2004
• Status: Expired due to Fees

• Current Assignee: Alliance For Sustainable Energy LLC
• Original Assignee: Alliance For Sustainable Energy LLC
• Inventors: Wanlass, Mark W., Carapella, Jeffrey J., Steiner, Myles A.
• Primary Examiner(s): Pillay, Devina
• Application Number:
  US12/992,871
• Publication Number:
  US 20110186115A1
• Time in Patent Office: 1,986 Days
• Field of Search: 136/255, 438/57
• US Class Current: 136/255
• CPC Class Codes: H01L 31/02168 the coatings being antireflective or having enhancing optical properties for the solar cells
• CPC Class Codes: H01L 31/022425 for solar cells
• CPC Class Codes: H01L 31/032 including, apart from doping materials or other impurities, only compounds not provided for in groups H01L31/0272 - H01L31/0312
• CPC Class Codes: H01L 31/065 the potential barriers being only of the graded gap type
• CPC Class Codes: H01L 31/068 the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
• CPC Class Codes: H01L 31/06875 inverted grown metamorphic [IMM] multiple junction solar cells, e.g. III-V compounds inverted metamorphic multi-junction cells
• CPC Class Codes: H01L 31/0693 the devices including, apart from doping material or other impurities, only AIIIBV compounds, e.g. GaAs or InP solar cells
• CPC Class Codes: H01L 31/1844 comprising ternary or quaternary compounds, e.g. Ga Al As, In Ga As P
• CPC Class Codes: H01L 31/1892 methods involving the use of temporary, removable substrates
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials
• CPC Class Codes: Y02E 10/547 Monocrystalline silicon PV cells

Abstract

High performance, high bandgap, lattice-mismatched, photovoltaic cells (10), both transparent and non-transparent to sub-bandgap light, are provided as devices for use alone or in combination with other cells in split spectrum apparatus or other applications.

Claims

1. A method of fabricating a high bandgap GaInP photovoltaic converter, comprising:

providing a crystalline growth structure having a growth surface that has a lattice constant which matches a relaxed lattice constant of a GaInP alloy that has a bandgap greater than that of Ga_0.51In_0.49P, wherein the crystalline growth structure comprises a graded GaAsP structure with a base surface having a lattice constant matching that of GaAs and where the growth surface comprises a GaAs_1-xP_x alloy;

growing a front contact layer on the growth surface;

growing a GaInP photovoltaic cell on the front contact layer, the GaInP photovoltaic cell having a relaxed lattice constant matching the lattice constant of the growth surface; and

growing a back contact layer on the GaInP photovoltaic cell.

2. The method of claim 1, wherein the front contact layer is a doped GaAsP front contact layer, the method further including:

doping the GaAsP front contact layer as a n-type dopant for an emitter in the GaInP cell, growing an initial thickness of the GaInP cell with no dopant, and growing the remainder of the GaInP cell with a p-type dopant to form a base portion of the GaInP cell while allowing the n-type dopant diffuse from the GaAsP front contact layer into the undoped thickness of the GaInP cell to form an emitter portion of the GaInP cell.

3. The method of claim 2, including growing the GaInP cell in a process that involves an elevated temperature sufficiently high to induce the diffusion of the dopant from the GaAsP front contact layer into the GaInP cell.

4. The method of claim 3, wherein the elevated temperature is in a range of about 600-750°

C.

5. The method of claim 2, including doping only a portion of the GaAsP front contact layer with the n-type dopant for the GaInP, said portion of the GaAsP being a spaced distance away from the base portion.

6. The method of claim 1, wherein providing the crystalline growth structure further comprises:

growing a graded layer of GaAs_1-xP_x on a crystalline parent substrate by starting the GaAs_1-xP_x the graded layer with a value of “

x”

that proportions the As and P in the GaAs_1-xP_x in a manner that provides the GaAs_1-xP_x with a lattice constant that matches the lattice constant of the parent substrate and ends with a value of “

x”

that proportions the Ga and P in the GaAs_1-xP_x in a manner that provides the GaAs_1-xP_x with a growth plane lattice constant that matches a relaxed lattice constant of GaInP with a target bandgap between about 1.9 eV and 2.2 eV.

7. The method of claim 6, wherein the parent substrate is GaAs.

8. The method of claim 7, wherein the graded GaAs_1-xP_x comprises 6 to 10 steps of GaAs_1-xp_x, each step being about 1.0 to 2.2 μ

m thick, with the phosphorus content increased, and the As content correspondingly decreased, by approximately 4 to 6 percent per step, and with the last step being approximately 30 to 44 percent phosphorus,

9. The method of claim 6, wherein the front contact layer is a doped GaAsP front contact layer and the back contact layer is a doped GaAsP back contact layer, the method further including:

growing a front passivation/window layer between the doped GaAsP front contact layer and an emitter of the GaInP cell and growing a back side confinement layer between a base of the GaInP cell and the doped GaAsP back contact layer.

10. The method of claim 9, including affixing a metal front contact grid on the doped GaAsP front contact layer, removing the doped GaAsP front contact layer from openings between portions of the metal front contact grids, applying a front anti-reflection coating on the passivation/window layer, mounting the metal front contact grid on a transparent handle, removing the parent substrate and the graded layer, affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer between portions of the metal back contact grid, and applying a back anti-reflection coating on the back surface confinement layer.

11. The method of claim 10, wherein removing the parent substrate and the graded layer further comprises:

growing an etch-stop layer between graded layer and the GaAsP back contact layer;

removing the parent substrate and graded layer by etching them away with an etchant that is selective for the substrate and graded layer and does not react with the etch-stop layer; and

then

removing the etch-stop layer.

12. The method of claim 11, including growing the cell upright.

13. The method of claim 11, including growing the cell inverted.

14. The method of claim 9, including affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer from openings between portions of the back contact grid, applying a back anti-reflection coating on the back surface confinement layer, mounting the metal back contact grid metal back contact grid metal back contact grid on a transparent handle, and removing the parent substrate and graded layer.

15. The method of claim 14, wherein removing the parent substrate and graded layer further comprises:

removing the parent substrate and graded layer by etching them away with an etchant that is selective for the parent substrate and graded layer and does not react with the etch-stop layer, and then removing the etch-stop layer.

16. The method of claim 15, including growing the cell upright.

17. The method of claim 15, including growing the cell inverted.

18. The method of claim 9, including affixing a metal front contact grid on the doped GaAsP front contact layer, removing the doped GaAsP front contact layer from openings between portions of the metal front contact grid, applying a front anti-reflection coating on the passivation/window layer, mounting the on an interim handle, removing the parent substrate and the graded layer, affixing a metal back contact grid on the doped GaAsP back contact layer, removing the doped GaAsP back contact layer from opening between portions of the metal back contact grid, applying a back anti-reflection coating on the back surface confinement layer, mounting the metal back contact grid on a permanent transparent handle, and removing the interim handle.