CCD-based multi-transistor active pixel sensor array

• US 8,772,698 B2
• Filed: 06/30/2011
• Issued: 07/08/2014
• Est. Priority Date: 06/30/2010
• Status: Active Grant

• Current Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Original Assignee: Life Technologies Corporation (Thermo Fisher Scientific Incorporated)
• Inventors: Fife, Keith, Milgrew, Mark
• Primary Examiner(s): Epps, Georgia Y
• Assistant Examiner(s): WILLIAMS, DON J
• Application Number:
  US13/174,245
• Publication Number:
  US 20120001056A1
• Time in Patent Office: 1,104 Days
• Field of Search: 250/214.1, 250/214.R, 250/214.A, 250/214.LA, 250/216, 250/208.1, 257/253, 204/406, 435/6.1, 435/283.1, 435/287.1, 435/287.2
• US Class Current: 250/214.R
• CPC Class Codes: C12Q 1/6869 Methods for sequencing
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: G01N 27/4143 Air gap between gate and channel, i.e. suspended gate [SG] FETs work function measurement per se G01N27/002
• CPC Class Codes: G01N 27/4145 specially adapted for biomolecules, e.g. gate electrode with immobilised receptors
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: G01N 33/00 Investigating or analysing materials by specific methods not covered by groups G01N1/00 - G01N31/00
• CPC Class Codes: G01R 29/26 Measuring noise figure; Measuring signal-to-noise ratio
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 29/66 Types of semiconductor device ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: Y10T 436/25875 Gaseous sample or with change of physical state

Abstract

A floating electrode is used to detect ions in close proximity to the electrode. The electrode is charge coupled to other electrodes and to other transistors to form a pixel that can be placed into an array for addressable readout. It is possible to obtain gain by accumulating charge into another electrode or onto a floating diffusion (FD) node or directly onto the column line. It is desirable to achieve both a reduction in pixel size as well as increase in signal level. To reduce pixel size, ancillary transistors may be eliminated and a charge storage node with certain activation and deactivation sequences may be used.

Claims

1. An ion sensitive (IS) accumulation pixel circuit to detect a chemical or a bio-chemical reaction, comprising:

a readout circuit;

an IS electrode;

at least two electrodes charge coupled to the IS electrode; and

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage, wherein the floating diffusion node is coupled to the readout circuit.

2. The IS accumulation pixel circuit of claim 1, wherein one of the at least two electrodes is a reference electrode configured to act as a barrier for charge packets.

3. The IS accumulation pixel circuit of claim 1, wherein one of the at least two electrodes is a reference electrode configured to act as a well for charge packets.

4. The IS accumulation pixel circuit of claim 1, wherein the readout circuit comprises one and only one transistor with a source coupled to both the floating diffusion node and a first column line and a drain coupled to a second column line.

5. The IS accumulation pixel circuit of claim 4, wherein a gate of the one and only one transistor is coupled to a second diffusion node in the IS accumulation pixel circuit.

6. The IS accumulation pixel circuit of claim 1, wherein the readout circuit comprises two and only two transistors, and wherein the two transistors comprise a reset transistor and a source follower transistor.

7. The IS accumulation pixel circuit of claim 6, wherein a source of the reset transistor is coupled to the floating diffusion node and a drain of the reset transistor is coupled to a second column line.

8. The IS accumulation pixel circuit of claim 7, wherein the source follower transistor has a gate coupled to the source of the reset transistor, and a drain coupled to the second column line.

9. The IS accumulation pixel circuit of claim 6, wherein the reset transistor has a source coupled to a second floating diffusion node, and a drain coupled to a second column line.

10. The IS accumulation pixel circuit of claim 9, wherein the source follower transistor has a source coupled to the floating diffusion node and a first column line, and a drain coupled to the first column line.

11. The IS accumulation pixel circuit of claim 6, wherein the reset transistor has a source coupled to the floating diffusion node, and a drain coupled a second column line.

12. The IS accumulation pixel circuit of claim 11, wherein the source follower transistor has a gate coupled to the source of the reset transistor, a drain coupled to the second column line and a source coupled to a first column line.

13. The IS accumulation pixel circuit of claim 1, wherein the readout circuit comprises a reset transistor, a source follower transistor and a row selection transistor.

14. The IS accumulation pixel circuit of claim 13, wherein the reset transistor has a source coupled to the floating diffusion node, and a drain coupled to a second column line.

15. The IS accumulation pixel circuit of claim 13, wherein the source follower transistor has a gate coupled to a source of the reset transistor, and a drain coupled to a second column line.

16. The IS accumulation pixel circuit of claim 13, wherein the row selection transistor has a drain coupled to a source of the source follower transistor, and a source coupled to a first column line.

17. The IS accumulation pixel circuit of claim 13, wherein a source of the row selection transistor is coupled to a sample and hold circuit via a buffer.

18. The IS accumulation pixel circuit of claim 13, wherein a source of the row selection transistor is coupled to a correlated double sampling circuit via a buffer.

19. A pixel array to detect a chemical or a bio-chemical reaction, comprising at least two IS accumulation pixel circuits, wherein each IS accumulation pixel circuit further comprises:

a readout circuit;

an IS electrode;

at least two electrodes charge coupled to the IS electrode; and

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage;

wherein the floating diffusion node is coupled to the readout circuit.

20. The pixel array of claim 19, wherein the readout circuit comprises one and only one transistor with a source coupled to both the floating diffusion node and a first column line and a drain coupled to a second column line.

21. The pixel array of claim 19, wherein the readout circuit comprises two and only two transistors, and wherein the two transistors comprise a reset transistor and a source follower transistor

22. The pixel array of claim 19, wherein the readout circuit comprises a reset transistor, a source follower transistor and a row selection transistor.

23. An ion sensitive (IS) accumulation pixel circuit to detect a chemical or a bio-chemical reaction, comprising:

an IS electrode;

at least two electrodes charge coupled to the IS electrode;

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage;

a reset transistor, having a source coupled to the floating diffusion node and a drain coupled to a fixed voltage; and

a transfer transistor, having a drain coupled to the source of the reset transistor.

24. A pixel array to detect a chemical or a bio-chemical reaction, comprising:

at least two ion sensitive accumulation pixel circuits, each comprising;

an IS electrode;

at least two electrodes charge coupled to the IS electrode;

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage;

a reset transistor, having a source coupled to the floating diffusion node and a drain coupled to a fixed voltage; and

a transfer transistor, having a drain coupled to the source of the reset transistor; and

a readout circuit, comprising;

a source follower transistor with a gate coupled to sources of the at least two ion sensitive accumulation pixel circuits; and

a row selection transistor with a gate coupled to a row line, a drain coupled to a source of the source follower transistor, and a source coupled to a column line.

25. An ion sensitive (IS) accumulation pixel circuit, comprising:

an IS electrode;

at least two electrodes charge coupled to the IS electrode;

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage; and

a transfer transistor, having a drain coupled to the floating diffusion node.

26. A pixel array, comprising:

at least two ion sensitive accumulation pixel circuits, each comprising;

an IS electrode;

at least two electrodes charge coupled to the IS electrode;

a floating diffusion node configured to convert an accumulated charge from the chemical or the bio-chemical reaction to a corresponding voltage; and

a transfer transistor, having a drain coupled to the floating diffusion node; and

a readout circuit, comprising;

a reset transistor with a source coupled to the drain of the transfer transistor;

a source follower transistor with a gate coupled to the drain of the transfer transistor; and

a row selection transistor with a gate coupled to a row line, a drain coupled to the source of the source follower transistor, and a source coupled to a column line.