Semiconductor device and method for manufacturing semiconductor device

• US 8,772,769 B2
• Filed: 10/05/2012
• Issued: 07/08/2014
• Est. Priority Date: 10/13/2011
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): SPALLA, DAVID C
• Application Number:
  US13/646,076
• Publication Number:
  US 20130092928A1
• Time in Patent Office: 641 Days
• Field of Search: 257/43, 257/288, 257/296, 257/368, 257/E21.409, 257/E29.255
• US Class Current: 257/43
• CPC Class Codes: H01L 21/461 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

To provide a miniaturized transistor having favorable electric characteristics. An oxide semiconductor layer is formed to cover a source electrode layer and a drain electrode layer, and then regions of the oxide semiconductor layer which overlap with the source electrode layer and the drain electrode layer are removed by polishing. Precise processing can be performed accurately because an etching step using a resist mask is not performed in the step of removing the regions of the oxide semiconductor layer overlapping with the source electrode layer and the drain electrode layer. Further, a sidewall layer having conductivity is provided on a side surface of a gate electrode layer in a channel length direction; thus, the sidewall layer having conductivity overlaps with the source electrode layer or the drain electrode layer with a gate insulating layer provided therebetween, and a transistor substantially including an L_ov region is provided.

Claims

1. A semiconductor device comprising:

a source electrode layer and a drain electrode layer;

an oxide semiconductor layer comprising a first impurity region in contact with a side surface of the source electrode layer, a second impurity region in contact with a side surface of the drain electrode layer, and a channel formation region between the first impurity region and the second impurity region;

a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

a gate electrode layer over the gate insulating layer;

a first conductive sidewall layer in contact with one side surface of the gate electrode layer; and

a second conductive sidewall layer in contact with the other side surface of the gate electrode layer,

wherein a length of an upper surface of the oxide semiconductor layer is longer than a length of a lower surface of the oxide semiconductor layer,

wherein at least part of the first conductive sidewall layer overlaps with the source electrode layer with the gate insulating layer therebetween, and

wherein at least part of the second conductive sidewall layer overlaps with the drain electrode layer with the gate insulating layer therebetween.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises crystals whose c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor layer.

3. The semiconductor device according to claim 1, wherein the oxide semiconductor layer comprises at least one material selected from indium or zinc.

4. The semiconductor device according to claim 3, wherein the oxide semiconductor layer further comprises at least one material selected from gallium, tin, hafnium, aluminum or zirconium.

5. The semiconductor device according to claim 1, wherein the first impurity region and the second impurity region comprise a material selected from phosphorus, arsenic, antimony, boron, aluminum, nitrogen, argon, helium, neon, indium, titanium, or zinc.

6. The semiconductor device according to claim 1, further comprising:

an insulating layer over the gate insulating layer, the first conductive sidewall layer, the second conductive sidewall layer, and the gate electrode layer;

a first wiring layer electrically connected to the source electrode layer through a first opening in the insulating layer and the gate insulating layer; and

a second wiring layer electrically connected to the drain electrode layer through a second opening in the insulating layer and the gate insulating layer.

7. The semiconductor device according to claim 6, wherein the insulating layer comprises aluminum oxide.

8. The semiconductor device according to claim 1, wherein the oxide semiconductor layer has a stacked-layer structure.

9. The semiconductor device according to claim 1, wherein the semiconductor device comprises a memory cell array including a plurality of memory cells.

10. A semiconductor device comprising:

a first transistor comprising a first gate electrode layer; and

a second transistor comprising;

a source electrode layer and a drain electrode layer, the source electrode layer being in contact with the first gate electrode layer;

an oxide semiconductor layer comprising a first impurity region in contact with a side surface of the source electrode layer, a second impurity region in contact with a side surface of the drain electrode layer, and a channel formation region between the first impurity region and the second impurity region;

a gate insulating layer over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer;

a second gate electrode layer over the gate insulating layer;

a first conductive sidewall layer in contact with one side surface of the second gate electrode layer; and

a second conductive sidewall layer in contact with the other side surface of the second gate electrode layer,

wherein a length of an upper surface of the oxide semiconductor layer is longer than a length of a lower surface of the oxide semiconductor layer,

wherein at least part of the first conductive sidewall layer overlaps with the source electrode layer with the gate insulating layer therebetween, and

wherein at least part of the second conductive sidewall layer overlaps with the drain electrode layer with the gate insulating layer therebetween.

11. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises crystals whose c-axis is aligned in a direction perpendicular to a surface of the oxide semiconductor layer.

12. The semiconductor device according to claim 10, wherein the oxide semiconductor layer comprises at least one material selected from indium or zinc.

13. The semiconductor device according to claim 12, wherein the oxide semiconductor layer further comprises at least one material selected from gallium, tin, hafnium, aluminum or zirconium.

14. The semiconductor device according to claim 10, further comprising:

a second insulating layer over the gate insulating layer, the first conductive sidewall layer, the second conductive sidewall layer, and the second gate electrode layer;

an electrode layer electrically connected to the drain electrode layer through an opening in the gate insulating layer and the second insulating layer; and

a wiring over the second insulating layer, electrically connected to the drain electrode layer through the electrode layer.

15. The semiconductor device according to claim 14, wherein the second insulating layer comprises aluminum oxide.

16. The semiconductor device according to claim 10, wherein the oxide semiconductor layer has a stacked-layer structure.

17. The semiconductor device according to claim 10, wherein the semiconductor device comprises a memory cell array including a plurality of memory cells.

18. The semiconductor device according to claim 10, wherein the first transistor is a silicon transistor.