Trench poly ESD formation for trench MOS and SGT

• US 8,772,828 B2
• Filed: 06/06/2013
• Issued: 07/08/2014
• Est. Priority Date: 01/20/2011
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Chang, Hong, Chen, John
• Primary Examiner(s): TRAN, MINH LOAN
• Application Number:
  US13/911,871
• Publication Number:
  US 20130299872A1
• Time in Patent Office: 397 Days
• Field of Search: 257/173, 257/328, 257/330, 257/E29.262
• US Class Current: 257/173
• CPC Class Codes: H01L 27/0259 using bipolar transistors as protective elements
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor material disposed in a trench with polysilicon lining at least the bottom of the trench. The semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

Claims

1. A semiconductor device, comprising:

a semiconductor material disposed in a trench in a semiconductor substrate, wherein the semiconductor material is located at least at a bottom of the trench, wherein the semiconductor material includes differently doped regions configured as a PNP or NPN structure formed in the trench with differently doped regions located side by side across a width of the trench.

2. The device of claim 1, further comprising an additional semiconductor device formed in additional trenches in the semiconductor substrate.

3. The device of claim 1, wherein the additional semiconductor device is metal oxide semiconductor field effect transistor (MOSFET) or insulated gate bipolar transistor (IGBT).

4. The device of claim 1, wherein the N-P-N or P-N-P structure is part of an electrostatic discharge (ESD) protection structure for the additional semiconductor device, wherein the first and second portions of the semiconductor material are electrically connected to the additional semiconductor device.

5. The device of claim 4, wherein the additional semiconductor device includes a source and a gate, wherein one side of ESD protection structure is connected to source, the other side is connected to gate.

6. The device of claim 5, wherein the additional semiconductor device is a shielded gate transistor (SGT) device having a shield electrode formed in a common trench with the gate, wherein the gate is electrically isolated from the shield electrode by an inter-electrode dielectric.

7. The device of claim 1, wherein the PNP or NPN structure includes first doped semiconductor regions along sidewalls of the trench and an oppositely-doped second semiconductor region located between the first semiconductor regions with a dielectric material filling a gap between the first semiconductor regions and above the second semiconductor region.

8. The device of claim 1, wherein the semiconductor material disposed in the trench is polysilicon.

9. The device of claim 1, further comprising an insulator material lining the bottom and sidewalls of the trench between the semiconductor material disposed in the trench and the semiconductor substrate.