Memory device comprising an array portion and a logic portion

• US 8,772,840 B2
• Filed: 06/18/2012
• Issued: 07/08/2014
• Est. Priority Date: 03/02/2006
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Tran, Tony
• Application Number:
  US13/525,730
• Publication Number:
  US 20120256272A1
• Time in Patent Office: 750 Days
• Field of Search: 257/216, 257/390, 257/E27.06
• US Class Current: 257/216
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells

Abstract

In an embodiment of the present invention, a method comprises patterning a first plurality of semiconductor structures in an array portion of a semiconductor substrate using a first photolithographic mask. The method further comprises patterning a second plurality of semiconductor structures over a logic portion of a semiconductor substrate using a second photolithographic mask. The method further comprises patterning a sacrificial layer over the first plurality of semiconductor structures using the second photolithographic mask. The sacrificial layer is patterned simultaneously with the second plurality of semiconductor structures.

Claims

1. A memory device comprising:

a substrate having an array portion and a logic portion;

a first plurality of transistor devices including a plurality of semiconductor structures that are recessed in the array portion of the substrate, wherein source and drain regions define at least part of an upper surface of each of the plurality of semiconductor structures, wherein the source and drain regions are co-planar with an uppermost surface of the substrate in the logic portion, and each of the plurality of semiconductor structures include a channel portion that is contiguous with the substrate array portion and adjacent to a gate region; and

a second plurality of transistor devices formed over the logic portion of the substrate, wherein each of the second plurality of transistor devices include a gate oxide layer, a conductive gate layer, and sidewall spacer structures, wherein there is no dielectric layer between the sidewall spacer structures, and wherein the second plurality of transistor devices are formed in a layer that is above the plurality of semiconductor structures,

wherein each of the plurality of semiconductor structures occupies an area of the substrate array portion between about 4F² and about 8F², wherein F is the minimum resolvable feature size formable using a photolithographic technique that is used to define features of the semiconductor structures, and

wherein each of the plurality of semiconductor structures occupies an area of the substrate having a length dimension that is equal to a width dimension.

2. The memory device of claim 1, wherein the channel portion is between a first and second gate region.

3. The memory device of claim 1, wherein the channel portion is U-shaped.

4. The memory device of claim 3, wherein each of the semiconductor structures comprises a first pillar and a second pillar, and each of the first plurality of transistor devices comprises a first source/drain region positioned atop the first pillar, and a second source/drain region positioned atop the second pillar, wherein the U-shaped channel connects the first and second source/drain regions.

5. The memory device of claim 1, wherein the plurality of semiconductor structures are defined by a pattern of alternating deep and shallow trenches that are crossed by a pattern of intermediate-depth trenches.

6. The memory device of claim 5, wherein the alternating deep and shallow trenches are filled with an oxide material.

7. The memory device of claim 5, wherein the alternating deep and shallow trenches are filled with a spin-on dielectric material.

8. The memory device of claim 5, wherein the shallow trenches are at least partially filled with a semiconductor material.

9. The memory device of claim 1, wherein the conductive gate layer comprises polycrystalline silicon.

10. The memory device of claim 1, wherein the plurality of semiconductor structures form a pattern having a first pitch, and wherein the second plurality of transistor devices form a pattern having a second pitch that is at least two times the first pitch.

11. The memory device of claim 1, wherein the second plurality of transistor devices are formed using a photolithographic mask that is also simultaneously used to pattern at least a portion of the plurality of semiconductor structures recessed in the array portion of the substrate.

12. The memory device of claim 1, wherein the substrate comprises single crystal silicon.

13. The memory device of claim 1, wherein the second plurality of transistor devices formed over the logic portion of the substrate are planar transistor devices.

14. The memory device of claim 1, wherein the second plurality of transistor devices formed over the logic portion of the substrate include a silicide region positioned over the conductive gate layer.

15. The memory device of claim 14, wherein the silicide region comprises a material selected from the group consisting of tungsten silicide and titanium silicide.