Semiconductor memory device

• US 8,772,849 B2
• Filed: 03/02/2012
• Issued: 07/08/2014
• Est. Priority Date: 03/10/2011
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Noda, Kosei
• Primary Examiner(s): Quach, Tuan N.
• Application Number:
  US13/410,608
• Publication Number:
  US 20120228687A1
• Time in Patent Office: 858 Days
• Field of Search: 257/43, 257/296, 257/368, 257/E27.06, 257/E27.084
• US Class Current: 257/296
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 41/70 the floating gate being an electrode shared by two or more components

Abstract

A semiconductor memory device includes a semiconductor film; a first gate insulating film covering the semiconductor film; a first gate electrode provided over the semiconductor film with the first gate insulating film interposed therebetween; a first conductive film which is provided over the first gate insulating film; an insulating film which is provided over the first gate insulating film, exposes top surfaces of the first gate electrode and the first conductive film, and has a groove portion between the first gate electrode and the first conductive film; an oxide semiconductor film which is provided over the insulating film and is in contact with the first gate electrode, the first conductive film, and the groove portion; a second gate insulating film covering the oxide semiconductor film; and a second gate electrode provided over the oxide semiconductor film and the groove portion with the second gate insulating film interposed therebetween.

Claims

1. A semiconductor memory device comprising:

a semiconductor layer;

a first gate insulating layer over the semiconductor layer;

an insulating layer over the first gate insulating layer;

a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;

a conductive layer provided in the insulating layer;

an oxide semiconductor layer in contact with the first gate electrode, the conductive layer, and side surfaces of a groove portion in the insulating layer;

a second gate insulating layer covering the oxide semiconductor layer; and

a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween.

2. The semiconductor memory device according to claim 1, wherein the groove portion is provided between the first gate electrode and the conductive layer.

3. The semiconductor memory device according to claim 1, wherein a top surface of the first gate electrode and a top surface of the conductive layer are aligned with a surface of the insulating layer.

4. The semiconductor memory device according to claim 1, wherein the oxide semiconductor layer is in contact with a bottom surface of the groove portion.

5. The semiconductor memory device according to claim 1, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the conductive layer seen from the above.

6. The semiconductor memory device according to claim 1, wherein the conductive layer is formed from the same layer and of the same material as the first gate electrode.

7. The semiconductor memory device according to claim 1, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.

8. A semiconductor memory device comprising:

a semiconductor layer;

a first gate insulating layer over the semiconductor layer;

an insulating layer over the first gate insulating layer;

a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;

a first conductive layer provided in the insulating layer;

an oxide semiconductor layer in contact with the first gate electrode, the first conductive layer, and side surfaces of a groove portion in the insulating layer;

a second gate insulating layer covering the oxide semiconductor layer;

a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween; and

a capacitor comprising a second conductive layer formed from the same layer and of the same material as the second gate electrode,

wherein the oxide semiconductor layer and the second gate insulating layer are interposed between the second conductive layer and the first gate electrode.

9. The semiconductor memory device according to claim 8, wherein the groove portion is provided between the first gate electrode and the first conductive layer.

10. The semiconductor memory device according to claim 8, wherein a top surface of the first gate electrode and a top surface of the first conductive layer are aligned with a surface of the insulating layer.

11. The semiconductor memory device according to claim 8, wherein the oxide semiconductor layer is in contact with a bottom surface of the groove portion.

12. The semiconductor memory device according to claim 8, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the first conductive layer seen from the above.

13. The semiconductor memory device according to claim 8, wherein the first conductive layer is formed from the same layer and of the same material as the first gate electrode.

14. The semiconductor memory device according to claim 8, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.

15. A semiconductor memory device comprising:

a semiconductor layer;

a first gate insulating layer over the semiconductor layer;

an insulating layer over the first gate insulating layer;

a first gate electrode over the semiconductor layer with the first gate insulating layer interposed therebetween, wherein the first gate electrode is provided in the insulating layer;

a conductive layer provided in the insulating layer;

an oxide semiconductor layer in contact with the first gate electrode, the conductive layer, side surfaces of a groove portion in the insulating layer, and the first gate insulating layer;

a second gate insulating layer covering the oxide semiconductor layer; and

a second gate electrode provided over the oxide semiconductor layer with the second gate insulating layer interposed therebetween.

16. The semiconductor memory device according to claim 15, wherein the groove portion is provided between the first gate electrode and the conductive layer.

17. The semiconductor memory device according to claim 15, wherein a top surface of the first gate electrode and a top surface of the conductive layer are aligned with a surface of the insulating layer.

18. The semiconductor memory device according to claim 15, wherein a depth of the groove portion is at least one-half of a distance between the first gate electrode and the conductive layer seen from the above.

19. The semiconductor memory device according to claim 15, wherein the conductive layer is formed from the same layer and of the same material as the first gate electrode.

20. The semiconductor memory device according to claim 15, wherein the oxide semiconductor layer comprises a crystal having a c-axis substantially perpendicular to a surface of the oxide semiconductor layer.