Vertical channel memory and manufacturing method thereof and operating method using the same

• US 8,772,858 B2
• Filed: 04/17/2007
• Issued: 07/08/2014
• Est. Priority Date: 10/11/2006
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Lue, Hang-Ting, Hsu, Tzu-Hsuan
• Primary Examiner(s): Luke, Daniel
• Assistant Examiner(s): Crawford, Latanya N
• Application Number:
  US11/785,322
• Publication Number:
  US 20080087942A1
• Time in Patent Office: 2,639 Days
• Field of Search: 257/324, 257/E29.309
• US Class Current: 257/324
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A vertical channel memory including a substrate, a channel, a multi-layer structure, a gate, a first terminal and a second terminal is provided. The channel protrudes from the substrate and has a top surface and two vertical surfaces. The multi-layer structure is disposed on the two vertical surfaces of the channel. The gate straddling multi-layer structure is positioned above the two vertical surfaces of the channel. The first terminal and the second terminal are respectively positioned at two sides of the channel opposing to the gate.

Claims

1. A memory device, comprising:

a substrate including a plurality of ridge shaped semiconductor protrusions, a plurality of channels in the plurality of ridge shaped semiconductor protrusions, wherein the ridge shaped semiconductor protrusions have top surfaces and the channels have two vertical surfaces on the corresponding ridge shaped semiconductor protrusions;

a BE-SONOS multi-layer structure disposed over the plurality of ridge shaped semiconductor protrusions including on the top surfaces and the two vertical surfaces of the channels in the plurality of channels and over the substrate between the plurality of ridge shaped semiconductor protrusions, the multi-layer structure including a first barrier layer on the channel, a tunneling layer, a second barrier layer, a dielectric charge trapping layer storing data with one of at least a programmed state and an erased state, and a third barrier layer stacked sequentially; and

a plurality of gates over the multi-layer structure and positioned above the two vertical surfaces of the channels.

2. The memory device of claim 1, wherein first pad areas on the ends of each of the ridge shaped semiconductor protrusions are separate from second pad areas on the ends of each of the other ridge shaped semiconductor protrusions.

3. The memory device of claim 1, wherein the first barrier layer, the second barrier layer and the third barrier layer are oxide layers, the charge trapping layer is a nitride layer, and the tunneling layer is a nitride layer or a polysilicon layer.

4. The memory device of claim 1, wherein the thickness of the first barrier layer is less than 20 angstrom (Å

).

5. The memory device of claim 1, wherein the thickness of the first barrier layer ranges between 5 Å

-20 Å

.

6. The memory device of claim 1, wherein the thickness of the first barrier layer is less than 15 Å

.

7. The memory device of claim 1, wherein the thickness of the first barrier layer ranges between 10 Å

-20 Å

.

8. The memory device of claim 1, wherein the thickness of the first barrier layer ranges between 10 Å

-15 Å

.

9. The memory device of claim 1, wherein the thickness of the tunneling layer is less than 20 Å

.

10. The memory device of claim 1, wherein the thickness of the tunneling layer ranges between 10 Å

-20 Å

.

11. The memory device of claim 1, wherein the thickness of the second barrier layer is less than 20 Å

.

12. The memory device of claim 1, wherein the thickness of the second barrier layer ranges between 15 Å

-20 Å

.

13. The memory device of claim 1, further comprising a thick oxide layer positioned on the substrate between the ridge shaped semiconductor protrusions in the plurality of ridge shaped semiconductor protrusions, wherein the thick oxide layer contacts the two vertical surfaces of the channels.

14. The memory device of claim 1, further comprising a cap layer disposed on top surfaces of the plurality of channels, wherein the cap layer substantially has the same width as that of the ridge shaped semiconductor protrusions.

15. The memory device of claim 1, wherein the substrate is a bulk silicon substrate or a silicon on insulator (SOI) substrate.

16. The memory device of claim 1, wherein the material of the plurality of gates is N+ polysilicon, P+ polysilicon or metal.

17. The memory device of claim 1, wherein the line width of the channel approximately ranges between 10 nm-60 nm.

18. The memory device of claim 14, wherein the cap layer comprises a silicon dioxide (SiO₂) layer and a silicon nitride (SiN) layer, and the silicon nitride layer is positioned on the silicon dioxide layer, such that the cap layer avails the formation of the vertical channel memory.

19. The memory device of claim 18, wherein the cap layer has a first width before trimming of the silicon nitride (SiN) layer and has a second width after the trimming wherein the first width is wider than the second width.

20. A memory device, comprising:

a substrate including a plurality of ridge shaped semiconductor protrusions, a plurality of channels in the plurality of ridge shaped semiconductor protrusions, wherein the ridge shaped semiconductor protrusions have top surfaces and the channels have two vertical surfaces on the corresponding ridge shaped semiconductor protrusions;

a multi-layer structure disposed over the plurality of ridge shaped semiconductor protrusions including on the top surfaces and the two vertical surfaces of the channels in the plurality of channels and over the substrate between the plurality of ridge shaped semiconductor protrusions, the multi-layer structure including a first barrier layer on the channel, a tunneling layer having a thickness of less than 20 Å and

being unable to store data with one of at least a programmed state and an erased state, a second barrier layer, a dielectric charge trapping layer and a third barrier layer stacked sequentially; and

a plurality of gates over the multi-layer structure and positioned above the two vertical surfaces of the channels.