MOS transistor structure

• US 8,772,865 B2
• Filed: 09/26/2012
• Issued: 07/08/2014
• Est. Priority Date: 09/26/2012
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Pearse, Jeffrey, Venkatraman, Prasad, Sellers, James, Bhatt, Hemanshu D.
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US13/627,912
• Publication Number:
  US 20140084363A1
• Time in Patent Office: 650 Days
• Field of Search: 257/330, 257/328, 257/331, 257/332.333, 257/329, 257/334, 257/E29.262, 257/E21.093, 438/270, 438/478, 438/589
• US Class Current: 257/331
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In one embodiment, an MOS transistor is formed to have an active region and a termination region. Within the termination region a plurality of conductors are formed to make electrical contact to conductors that are within a plurality of trenches. The plurality of conductors in the termination region are formed to be substantially coplanar.

Claims

1. An MOS transistor comprising:

a semiconductor substrate having a surface;

an active region of the MOS transistor;

a plurality of active trenches formed in the semiconductor substrate and within the active region wherein each active trench of the plurality of active trenches includes a shield conductor and an overlying gate conductor;

a source region formed as a first doped region on the surface of the semiconductor substrate adjacent to each active trench;

a termination region that is external to the active region;

a shield contact trench formed in the semiconductor substrate and within the termination region, the shield contact trench having a first conductor within the shield contact trench;

a gate contact trench formed in the semiconductor substrate and positioned near both the shield contact trench and at least one active trench of the plurality of active trenches, the gate contact trench having a second conductor within the gate contact trench and wherein no source region is adjacent to the gate contact trench;

a source conductor overlying the plurality of active trenches and forming electrical contact to the source region of each active trench of the plurality of active trenches;

a third conductor overlying the shield contact trench and forming electrical contact to the first conductor; and

a fourth conductor overlying the gate contact trench and forming electrical contact the second conductor wherein the third conductor and the fourth conductor are substantially coplanar not electrically connected together.

2. The MOS transistor of claim 1 further including an insulator underlying the third conductor and the fourth conductor wherein the third conductor forms electrical contact to the first conductor through a first opening in the insulator and the fourth conductor forms electrical contact to the second conductor through a second opening in the insulator.

3. The MOS transistor of claim 2 further including a fifth conductor on the fourth conductor and a sixth conductor on the third conductor.

4. The MOS transistor of claim 1 further including a fifth conductor underlying the surface and extending from the first conductor to the shield conductor of at least one active trench of the plurality of active trenches and electrically connecting the first conductor to the shield conductor of the at least one active trench.

5. The MOS transistor of claim 1 further including a second doped region on the surface of the semiconductor substrate wherein each source region is formed within the second doped region and wherein the plurality of active trenches and the gate contact trench extend through the second doped region into the semiconductor substrate.

6. The MOS transistor of claim 1 wherein the third conductor and the fourth conductor are inter-digitated.

7. The MOS transistor of claim 1 wherein the second conductor within the gate contact trench makes electrical contact to the gate conductor of each active trench of the plurality of active trenches.

8. The MOS transistor of claim 7 wherein the gate contact trench includes a shield conductor underlying and electrically isolated from the second conductor and wherein the first conductor within the shield contact trench makes electrical contact to the shield conductor of each active trench of the plurality of active trenches and to the shield conductor within the gate contact trench.