Superjunction structures for power devices and methods of manufacture

• US 8,772,868 B2
• Filed: 04/27/2011
• Issued: 07/08/2014
• Est. Priority Date: 04/27/2011
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Rinehimer, Mark L., Yilmaz, Hamza, Pan, James, Shenoy, Praveen Muraleedharan, Ridley, Rodney S. Sr.
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US13/095,670
• Publication Number:
  US 20120273875A1
• Time in Patent Office: 1,168 Days
• Field of Search: 257/220, 257/221, 257/242, 257/244, 257/502, 257/E21.38, 257/E21.382
• US Class Current: 257/341
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/66136 PN junction diodes
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/8611 Planar PN junction diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A power device includes a semiconductor substrate having a plurality of alternately arranged pillars of first and second conductivity types. At least one of the plurality of pillars of second conductivity type includes a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench, a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type.

Claims

1. A power device comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer of the first conductivity type disposed on the semiconductor substrate;

a first trench disposed in the epitaxial layer of the first conductivity type;

a second trench disposed in the epitaxial layer of the first conductivity type; and

a mesa disposed between the first trench and the second trench, the mesa defining a pillar of the first conductivity type from the epitaxial layer of the first conductivity type;

a body region of a second conductivity type disposed in the epitaxial layer of the first conductivity type;

a source region of the first conductivity type disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region,

the first trench including a first pillar of the second conductivity type,

the second trench including a second pillar of the second conductivity type, the second pillar of the second conductivity type including;

a first trench epitaxial layer of the second conductivity type disposed on a trench sidewall of the second trench and a trench bottom surface of the second trench,

a second trench epitaxial layer of the second conductivity type disposed on the first trench epitaxial layer of the second conductivity type, and

an insulating material layer disposed on the second trench epitaxial layer of the second conductivity type,

the first pillar of the second conductivity type and the second pillar of the second conductivity type forming pillars of alternating conductivity type with the pillar of the first conductivity type.

2. The power device of claim 1, wherein the epitaxial layer of the first conductivity type includes a plurality of epitaxial layers of the first conductivity type.

3. The power device of claim 1, wherein the insulating material layer includes a thermal oxide.

4. The power device of claim 1, wherein a doping concentration of the second epitaxial layer of the second conductivity type has a lower doping concentration than a doping concentration of the first epitaxial layer of the second conductivity type.

5. A power device comprising:

a first N-type epitaxial layer disposed on a substrate;

a second N-type epitaxial layer disposed on the first N-type epitaxial layer;

a first trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer;

a second trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer; and

a mesa disposed between the first trench and the second trench, the mesa defining an N-type pillar from the first N-type epitaxial layer and the second N-type epitaxial layer,

the first trench including a first P-type pillar,

the second trench including a second P-type pillar,

the first P-type pillar and the second P-type pillar forming pillars of alternating conductivity type with the N-type pillar,

each P-type pillar including;

a first trench epitaxial layer disposed on a trench sidewall and a trench bottom surface; and

a second trench epitaxial layer disposed on the first trench epitaxial layer, the first trench epitaxial layer including an N-type epitaxial layer having a doping concentration that is lower than a doping concentration of the second trench epitaxial layer, the second trench epitaxial layer including a P-type epitaxial layer.

6. The power device of claim 5, wherein each P-type pillar further includes a conductive material layer disposed on the second trench epitaxial layer.

7. The power device of claim 6, wherein:

the second trench epitaxial layer has a doping concentration that is higher than a doping concentration of the first trench epitaxial layer; and

the conductive material layer has a doping concentration that is higher than the doping concentration of the second trench epitaxial layer.

8. The power device of claim 6, wherein the conductive material layer includes an N-type layer that has a doping concentration that is lower than a doping concentration of the second trench epitaxial layer.

9. The power device of claim 6, wherein the conductive material layer includes an intrinsic epitaxial layer.

10. The power device of claim 6, wherein the conductive material layer includes polysilicon.

11. The power device of claim 5, wherein the first N-type epitaxial layer includes intrinsic silicon.

12. The power device of claim 5, further comprising:

a first P-enrichment region disposed at a bottom of the first P-type pillar and

a second P-enrichment region disposed at a bottom of the second P-type pillar.

13. The power device of claim 5, wherein the N-type pillar includes an upper N-region, a middle N-region and a lower N-region, the upper N-region has a doping concentration that is lower than a doping concentration of the middle N-region, and the doping concentration of the middle N-region is lower than a doping concentration of the lower N-region.

14. The power device of claim 5, further comprising:

a P-type body region disposed in the second N-type epitaxial layer;

an N-type source region disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the N-type source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region.

15. The power device of claim 14, wherein the source metal layer is in electrical contact with the first P-type pillar and the second P-type pillar.

16. A power device comprising:

a first N-type epitaxial layer disposed on a substrate;

a second N-type epitaxial layer disposed on the first N-type epitaxial layer;

a first trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer;

a second trench extending through the second N-type epitaxial layer and terminating within the first N-type epitaxial layer; and

a mesa disposed between the first trench and the second trench, the mesa defining an N-type pillar from the first N-type epitaxial layer and the second N-type epitaxial layer,

the first trench including a first P-type pillar,

the second trench including a second P-type pillar,

the first P-type pillar and the second P-type pillar forming pillars of alternating conductivity type with the N-type pillar, and

the N-type pillar including an upper N-region, a middle N-region and a lower N-region, the upper N-region having a doping concentration that is lower than a doping concentration of the middle N-region, and the doping concentration of the middle N-region being lower than a doping concentration of the lower N-region.

17. The power device of claim 16, wherein the first N-type epitaxial layer includes intrinsic silicon.

18. The power device of claim 16, further comprising:

a first P-enrichment region disposed at a bottom of the first P-type pillar and

a second P-enrichment region disposed at a bottom of the second P-type pillar.

19. The power device of claim 16, further comprising:

a P-type body region disposed in the second N-type epitaxial layer;

an N-type source region disposed in the body region;

a gate electrode disposed on the body region and disposed on at least a portion of the N-type source region, the gate electrode being insulated from the body region and the source region; and

a source metal layer in electrical contact with the source region.

20. The power device of claim 19, wherein the source metal layer is in electrical contact with the first P-type pillar and the second P-type pillar.