Semiconductor interconnect structures

• US 8,772,938 B2
• Filed: 12/04/2012
• Issued: 07/08/2014
• Est. Priority Date: 12/04/2012
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Boyanov, Boyan, Singh, Kanwal, Clarke, James, Myers, Alan
• Primary Examiner(s): Smith, Zandra
• Assistant Examiner(s): PATTON, PAUL E
• Application Number:
  US13/693,598
• Publication Number:
  US 20140151893A1
• Time in Patent Office: 581 Days
• Field of Search: 257/758, 257/E21.576, 257/E21.577, 257/E21.579, 257/E21.582
• US Class Current: 257/758
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76883 Post-treatment or after-treatment of the conductive material
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 23/53228 the principal metal being copper
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. In some embodiments, an etch may be applied to an insulator layer having one or more conductive features therein, such that the insulator layer is recessed below the top of the conductive features and the edges of the conductive features are rounded or otherwise softened. A conformal etch stop layer may then be deposited over the conductive features and the insulator material. A second insulator layer may be deposited above the conformal etch stop layer, and an interconnect feature may pass through the second insulator layer and the conformal etch stop layer to connect with the rounded portion of one of the conductive features. In some embodiments, the interconnect feature is an unlanded via and the unlanded portion of the via may or may not penetrate through the conformal barrier layer.

Claims

1. A semiconductor device, comprising:

a first insulator structure;

a first conductive feature partially within the first insulator structure, the first conductive feature having a portion at least partially protruding beyond a surface of the first insulator structure;

a second insulator structure having a second conductive feature therein;

a conformal intervening layer between the first and second insulator structures, wherein the first insulator structure, intervening layer, and second insulator structure are arranged in a stack, and wherein the conformal intervening layer conforms to the protruding portion of the conductive feature of the first insulator structure; and

a conductive interconnect feature connecting the first conductive feature with the second conductive feature, the conductive interconnect feature passing through the conformal intervening layer and partially landing on the first conductive feature, wherein the unlanded portion of the conductive interconnect does not penetrate the conformal intervening layer.

2. The device of claim 1, wherein the first insulator structure comprises a deposition of ultra-low dielectric material through which the portion of the first conductive feature protrudes, the ultra-low dielectric material having a dielectric constant below that of silicon dioxide.

3. The device of claim 1, wherein the conductive interconnect feature is an unlanded via.

4. The device of claim 1, wherein the first insulator structure comprises a deposition of porous dielectric material through which the portion of the first conductive feature protrudes.

5. The device of claim 1, wherein the ratio of first insulator structure etch rate to first conductive feature etch rate for a given etch process is greater than 3.

6. The device of claim 1, wherein the conformal intervening layer is a conformal etchstop layer deposited over the first insulator structure and the first conductive feature, and the portion of the first conductive feature at least partially protruding beyond the surface of the first insulator structure has rounded corners.

7. The device of claim 1, further comprising an additional insulator layer between the conformal intervening layer and the second insulator structure and adjacent to sides of the protruding portion of the first conductive feature, wherein the conductive interconnect feature further passes through the additional insulator layer.

8. The device of claim 7, wherein the additional insulator layer is one of a flowable carbide or flowable nitride deposited over the conformal intervening layer.

9. The device of claim 7, wherein the additional insulator layer comprises an etchstop material, effectively increasing the thickness of portions of the conformal etchstop layer.

10. The device of claim 1, wherein the first and second insulator structures each comprise an ultra-low dielectric material having a dielectric constant below that of silicon dioxide, and the conformal intervening layer comprises a dielectric material having a higher dielectric constant than the ultra-low dielectric material.

11. A multilayer integrated circuit device, comprising:

a first insulator structure having one or more metal features within an insulator material, the one or more metal features having a portion at least partially protruding beyond a surface of the first insulator structure, the protruding portion having rounded corners;

a second insulator structure having one or more metal features embedded within an insulator material;

a conformal etchstop layer between the first and second insulator structures, wherein the first insulator structure, etchstop layer, and second insulator structure are arranged in a stack; and

a conductive interconnect feature connecting one of the metal features of the first insulator structure to one of the metal features of the second insulator structure, a portion of the conductive feature passing through the conformal etchstop layer and partially landing on at least one of the rounded corners of one of the metal features of the first insulator structure, wherein the unlanded portion of the conductive feature does not penetrate the conformal etchstop layer.

12. The device of claim 11, wherein the conductive interconnect feature is an unlanded via.

13. The device of claim 11, wherein the first insulator structure comprises a deposition of porous dielectric material through which the portion of the one or more metal features protrudes.

14. The device of claim 12, wherein the rounded corners of the one or more metal features increase the distance between the unlanded via and an adjacent metal feature, relative to the distance between those two if the adjacent metal feature were not partially rounded.

15. The device of claim 11, further comprising an additional insulator layer between the conformal etchstop layer and the second insulator structure.

16. The device of claim 15, wherein the additional insulator layer is one of a flowable carbide or flowable nitride material.

17. The device of claim 15, wherein the additional insulator layer comprises an etchstop material which effectively increases the thickness of the conformal etchstop layer between the one or more metal features of the first insulator structure.

18. A method of forming a semiconductor device, comprising:

providing a first insulator structure having a first metal feature within an insulator material;

etching the first insulator structure so as to recess the insulator material to be lower than the first metal feature and to round corners of the first metal feature;

depositing a conformal etchstop layer over the etched insulator material and the rounded first metal feature;

depositing a second insulator structure having a second metal feature embedded within an insulator material; and

connecting the first metal feature with the second metal feature with a partially landed conductive interconnect feature, wherein the unlanded portion of the unlanded conductive interconnect feature does not penetrate the conformal etchstop layer.

19. The method of claim 18, wherein the conductive interconnect feature is an unlanded via.

20. The method of claim 18, further comprising depositing an additional insulator layer between the conformal etchstop layer and the second insulator structure.

21. The method of claim 18, further comprising depositing a flowable barrier layer over the conformal etchstop layer before depositing the second insulator structure.

22. The method of claim 21, wherein the flowable barrier layer is one of a flowable carbide or flowable nitride material.

23. The method of claim 18, wherein etching the first insulator structure comprises applying an unmasked etch to the first insulator structure, wherein the etch rate of the insulator material is greater than the etch rate of the first metal feature.