Semiconductor device, image display device, storage device, and electronic device
First Claim
1. A semiconductor device comprising:
- a circuit including a selection transistor; and
a buffer circuit electrically connected to a gate of the selection transistor through a first signal line,wherein the buffer circuit comprises;
a first inverter and a second inverter that are sequentially connected in series; and
a bootstrap circuit,wherein an input terminal of the first inverter is electrically connected to an input signal line to which a selection signal is input,wherein an output terminal of the second inverter is electrically connected to the first signal line,wherein a high-potential input terminal of the first inverter is electrically connected to a second signal line to which a first potential is input,wherein low-potential input terminals of the first inverter and the second inverter are electrically connected to a third signal line to which a second potential lower than the first potential is input, andwherein the bootstrap circuit outputs a third potential higher than the first potential to a high-potential input terminal of the second inverter in response to the selection signal.
1 Assignment
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Accused Products
Abstract
To provide a semiconductor device with reduced power consumption that includes a selection transistor. To provide a semiconductor device capable of high-speed operation without increasing a power supply potential. A buffer circuit connected to a gate line has a function of generating a potential higher than a high power supply potential by using the high power supply potential and outputs the potential in response to a selection signal. Specifically, a bootstrap circuit boosts a high power supply potential that is input to an inverter that is the closest to an output side in the buffer circuit. Further, the bootstrap circuit boosts the potential when the gate line is selected, and does not boost the potential when the gate line is not selected.
118 Citations
20 Claims
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1. A semiconductor device comprising:
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a circuit including a selection transistor; and a buffer circuit electrically connected to a gate of the selection transistor through a first signal line, wherein the buffer circuit comprises; a first inverter and a second inverter that are sequentially connected in series; and a bootstrap circuit, wherein an input terminal of the first inverter is electrically connected to an input signal line to which a selection signal is input, wherein an output terminal of the second inverter is electrically connected to the first signal line, wherein a high-potential input terminal of the first inverter is electrically connected to a second signal line to which a first potential is input, wherein low-potential input terminals of the first inverter and the second inverter are electrically connected to a third signal line to which a second potential lower than the first potential is input, and wherein the bootstrap circuit outputs a third potential higher than the first potential to a high-potential input terminal of the second inverter in response to the selection signal. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor device comprising:
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a circuit including a selection transistor; and a buffer circuit electrically connected to a gate of the selection transistor through a first signal line, wherein the buffer circuit comprises; a first inverter and a second inverter that are sequentially connected in series; and a bootstrap circuit, wherein an input terminal of the first inverter is electrically connected to an input signal line to which a selection signal is input, wherein an output terminal of the second inverter is electrically connected to the first signal line, wherein a high-potential input terminal of the first inverter and an input terminal of the bootstrap circuit are electrically connected to a second signal line to which a first potential is input, wherein low-potential input terminals of the first inverter and the second inverter are electrically connected to a third signal line to which a second potential lower than the first potential is input, wherein an output terminal of the bootstrap circuit is electrically connected to a high-potential input terminal of the second inverter, and wherein the bootstrap circuit boosts the first potential when the selection signal is input to the buffer circuit. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A semiconductor device comprising:
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a circuit including a selection transistor; and a buffer circuit electrically connected to a gate of the selection transistor through a first signal line, wherein the buffer circuit comprises; first to n-th inverters that are sequentially connected in series; and a bootstrap circuit, wherein an input terminal of the first inverter is electrically connected to an input signal line to which a selection signal is input, wherein an output terminal of the n-th inverter is electrically connected to the first signal line, wherein high-potential input terminals of the first to (n−
1) th inverters are electrically connected to a second signal line to which a first potential is input,wherein low-potential input terminals of the first to n-th inverters are electrically connected to a third signal line to which a second potential lower than the first potential is input, and wherein the bootstrap circuit outputs a third potential higher than the first potential to a high-potential input terminal of the n-th inverter in response to the selection signal. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification