Integrated inductors

• US 8,773,233 B2
• Filed: 02/04/2013
• Issued: 07/08/2014
• Est. Priority Date: 06/29/2006
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Hazucha, Peter, Nguyen, Trang T., Schrom, Gerhard, Paillet, Fabrice, Gardner, Donald S., Moon, Sung T., Karnik, Tanay
• Primary Examiner(s): NGUYEN, TUYEN T
• Application Number:
  US13/758,881
• Publication Number:
  US 20130182365A1
• Time in Patent Office: 519 Days
• Field of Search: 336/65, 336/83, 336/200, 336/232, 257/531
• US Class Current: 336/200
• CPC Class Codes: H01F 17/0033 with the coil helically wound around a magnetic core
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01F 21/12 discontinuously variable, e.g. tapped
• CPC Class Codes: H01F 27/34 Special means for preventing or reducing unwanted electric or magnetic effects, e.g. no-load losses, reactive currents, harmonics, oscillations, leakage fields

Abstract

Multiple-inductor embodiments for use in substrates are provided herein.

Claims

1. An apparatus comprising:

at least two adjacent rows of embedded inductors with overlapping inductor areas, wherein adjacent inductors within the least two adjacent rows of inductors are complementary inductor pairs with overlapping inductor areas;

a plurality of switches coupled at one end of the least two adjacent rows of embedded inductors, the other end of the at least two adjacent rows of inductors coupled to a common output terminal; and

a capacitor coupled to the common output terminal.

2. The apparatus of claim 1, wherein a terminal of an inductor from the adjacent inductors being coupled to a terminal from another inductor from the adjacent inductors.

3. The apparatus of claim 1 further comprises a controller coupled to the plurality of switches.

4. The apparatus of claim 1, wherein the plurality of switches to drive the at least two adjacent rows of embedded inductors consecutively with a different phase.

5. The apparatus of claim 1, wherein each inductor of the embedded inductors has spaced apart vias.

6. The apparatus of claim 5, wherein the spaced apart vias are coupled together by a single conductive layer.

7. The apparatus of claim 5, wherein the spaced apart vias are coupled together by multiple conductive layers parallel to one another.